LTC1840
Dual Fan Controller
with 2-Wire Interface
FEATURES
s
s
s
s
s
DESCRIPTIO
s
s
s
s
s
s
s
s
Two 8-Bit Current DACs
DACs Guaranteed Monotonic
Known IC State on Power-Up
Serial Interface Watchdog Timer with Disable
2-Wire Serial Interface Compatible with I
2
C
TM
and SMBus
2 Programmable Fan Tachometer Interfaces
4 Programmable General Purpose I/Os
Small 16-Pin SSOP Package
Single 2.7V to 5.75V Supply Operation
Fault Output Signal
Status Register
Fan Blasting Function
Nine Addresses Using Two Programming Lines
The LTC
®
1840 is a fan controller with two 8-bit current
output DACs, two tachometer interfaces, and four general
purpose I/O (GPIO) pins. It operates from a single supply
with a range of 2.7V to 5.75V. A current output DAC is used
to control an external switching regulator, which controls
the fan speed. A current output DAC and tachometer allow
a controller to form a closed control loop on fan velocity.
The GPIO pins can be used as digital inputs or open drain
pull-down outputs.
The part features a simple 2-wire I
2
C and SMBus compat-
ible serial interface that allows communication between
many devices. The interface includes a fault status register
that reflects the state of the part and which can be polled
to find the cause of a fault condition. Other operational
characteristics of the part, such as DAC output currents,
GPIO modes, and tachometer frequency, are also pro-
grammed through the serial interface. Two address pins
provide nine possible device addresses.
The BLAST pin is provided to force the DAC output
currents to program the maximum regulator output
voltages through a single pin and gate the operation of the
serial access timer.
APPLICATIO S
s
s
s
s
Servers
Desktop Computers
Power Supplies
Cooling Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
I
2
C is a trademark of Philips Electronics N.V.
TYPICAL APPLICATIO
3.3V
3.3V
10k
FAULT
TO
MASTER
SDA
SCL
V
CC
Low Parts Count, High Efficiency Dual Fan Control
+
10µF
12V
0.1µF
V
IN
GPI04
BLAST
IDACOUTA
SYSTEM
RESET
RUN/SS SENSE
LTC1771
PGATE
I
TH
R
C1
10k
C
C1
220pF
V
FB
C
FB1
100pF
MODE
GND
UPS5817
R
SENSE1
0.05Ω
+
C
VIN1
22µF
R
FB1A
75k
Si6447DQ
L1 47µH
LTC1840
3.3V
12V
V
IN
R
SENSE2
0.05Ω
+
3.3V
130Ω
LED2
C
VIN2
22µF
130Ω
LED1
NC
NC
A0
A1
GPI01
GPI02
GND
GPI03
IDACOUTB
TACHB
TACHA
R
C2
10k
C
C2
220pF
RUN/SS SENSE
LTC1771
I
TH
PGATE
V
FB
C
FB2
100pF
MODE
GND
Si6447DQ
L2 47µH
UPS5817
ADDRESS = 1110010
(8 OTHERS POSSIBLE)
U
3.3V
DC
FAN
C
OUT1
150µF
10k
TACH
OUT
U
U
+
R
FB1B
28k
2-NMB 6820PL-04W-B29-D50 FANS
1.1A NOM AT 12V
3.3V
R
FB2A
75k
R
FB2B
28k
DC
FAN
C
OUT2
150µF
10k
TACH
OUT
+
1840 TA01
1840f
1
LTC1840
ABSOLUTE
(Note 1)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
SCL 1
SDA 2
A1 3
A0 4
FAULT 5
GPIO1 6
GPIO2 7
GND 8
16 V
CC
15 I
DACOUTA
14 I
DACOUTB
13 BLAST
12 TACHB
11 TACHA
10 GPIO4
9
GPIO3
V
CC
to GND .................................................... –0.3 to 6V
A0, A1 ............................................. –0.3 to (V
CC
+ 0.3V)
I
DACOUTA
, I
DACOUTB .............................
–0.3 to (V
CC
+ 0.75V)
All other pins ................................................. –0.3 to 6V
Operating Temperature
LTC1840C ............................................... 0°C to 70°C
LTC1840I .............................................–40°C to 85°C
Storage Temperature Range ..................–65°C to 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
LTC1840CGN
LTC1840IGN
GN PART
MARKING
1840
1840I
GN PACKAGE
16-LEAD PLASTIC SSOP
T
JMAX
= 125°C,
θ
JA
= 110°C/W
Consult LTC marketing for parts specified with wider operating temperature ranges.
The
q
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
CC
= 3V
SYMBOL
DACs
n
DNL
INL
ZSE
Resolution
Differential Nonlinearity
Integral Nonlinearity
Zero-Scale Error
Output Voltage Rejection
Output Voltage Rejection
I
DACOUTA(FS),
I
DACOUTB(FS)
Power Supply
V
CC
I
CC
V
UVLO
V
UVHYS
f
OSC
PSRR
GPIO Performance
I
O
V
IL
V
IH
V
IHYST
I
LEAK
Output Current Sink
Digital Input Low Voltage
Digital Input High Voltage
Input Hysteresis
Leakage
V
GPIOX
= 0.7V, Internal Pull-Down Enabled
Internal Pull-Down Disabled
Internal Pull-Down Disabled
(Note 2)
Internal Pull-Down Disabled
q
q
q
ELECTRICAL CHARACTERISTICS
PARAMETER
CONDITIONS
MIN
8
TYP
MAX
UNITS
Bits
V
DACOUT
= 1.1V, Guaranteed Monotonic
V
DACOUT
= 1.1V
V
DACOUT
= 1.1V
1.1V< V
DACOUT
< 3.75V
V
CC
= 5.75V, 1.1V < V
DACOUT
< 6.5V
Sinking
V
DACOUT
= 1.1V
q
±0.9
±
4
–0.2
0.1
2
±1
±2
97
95
2.7
400
500
103
105
5.75
600
750
2.69
160
53
0.5
Full-Scale Current
q
Positive Supply Voltage
Supply Current
UVLO/POR Voltage
UVLO/POR Voltage Hysteresis
Oscillator Frequency
Supply Sensitivity
2.7V < V
CC
< 5.75V
(Note 2)
V
CC
= 3V, A0 and A1 Floating
V
CC
= 5V, A0 and A1 Floating
q
q
2.1
20
2.4
90
50
0.1
Oscillator Performance
q
47
10
0.3V
CC
0.7V
CC
50
±1
2
U
LSB
LSB
µA
LSB
LSB
µA
µA
V
µA
µA
V
mV
kHz
%/V
mA
V
V
mV
µA
1840f
W
U
U
W W
W
LTC1840
The
q
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
CC
= 3V
SYMBOL
V
IH
V
IL
V
LTH
I
LEAK
C
IN
Digital Output SDA
V
OL
V
OL
V
IH
V
IL
I
LEAK
Digital Input BLAST
V
LTH
V
IHYST
I
LEAK
V
IH
V
IL
I
IN
f
I2C
t
BUF
t
hD, STA
t
su, STA
t
su, STO
t
hD, DAT
t
su, DAT
t
LOW
t
HIGH
t
f
t
r
Logic Threshold Voltage
Input Hysteresis
Digital Input Leakage
Input High Voltage
Input Low Voltage
Input Current
I
2
C Operating Frequency
Bus Free Time Between
Stop and Start Condition
Hold Time after (Repeated)
Start Condition
Repeated Start Condition
Setup Time
Stop Condition Setup Time
Data Hold Time
Data Setup Time
Clock Low Period
Clock High Period
Clock, Data Fall Time
Clock, Data Rise Time
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
Note 2:
Guaranteed by design not subject to test.
AX Shorted to GND or V
CC
, V
CC
= 5V
(Note 2)
(Note 2)
(Note 2)
(Note 2)
(Note 2)
0
4.7
4
4.7
4
300
250
4.7
4.0
300
1000
Measured on BLAST Falling Edge
(Note 2), Measured on Rising Edge
V
CC
= 5V and 0V, V
IN
= GND to V
CC
q
q
ELECTRICAL CHARACTERISTICS
PARAMETER
Digital Input High Voltage
Digital Input Low Voltage
Logic Threshold Voltage
Digital Input Leakage
Digital Input Capacitance
Digital Output Low Voltage
Digital Output Low Voltage
Digital Input High Voltage
Digital Input Low Voltage
Digital Input Leakage
CONDITIONS
q
q
MIN
1.4
TYP
MAX
UNITS
V
Digital Inputs SCL, SDA
0.6
1
±1
10
q
V
V
µA
pF
V
V
V
(Note 2)
V
CC
= 5V and 0V, V
IN
= GND to V
CC
(Note 2)
I
PULL-UP
= 3mA
I
PULL-UP
= 1mA
0.4
0.4
0.7V
CC
0.3V
CC
±1
0.95
20
±1
0.9V
CC
0.1V
CC
±100
100
1.0
1.05
Digital Output FAULT
q
Digital Inputs TACHA, TACHB
q
q
V
µA
V
mV
µA
V
V
µA
kHz
µs
µs
µs
µs
ns
ns
µs
µs
ns
ns
V
CC
= 5V and 0V, V
IN
= GND to V
CC
Address Inputs A0, A1
Timing Characteristics
Note 1:
Absolute Maximum Ratings are those values beyond
which the life of a device may be impaired.
1840f
3
LTC1840
TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Supply Voltage
550
T
A
= 25°C
450
440
100.05
I
DACOUT
(µA)
500
I
CC
(µA)
I
CC
(µA)
450
400
2.5
3.5
4.5
V
CC
(V)
5.5
I
DACOUT
FS vs V
DACOUT
at V
CC
= 3V to 5V
120
T
A
= 25°C
100
80
60
40
20
0
I
DACOUT
(µA)
I
DACOUT
(µA)
99.95
99.90
99.85
99.80
99.75
0.5
I
DACOUT
(µA)
0
1
2
3
V
DACOUT
(V)
4
I
DACOUT
AC Supply Rejection at
Full Scale, V
CC
= 3V DC
20
T
A
= 25°C
10
I
DACOUT
/V
CC
(µA/V)
15
DAC ZSE (nA)
DNL (LSB)
10
5
0
1
100
10
FREQUENCY (kHz)
4
U W
1840 G01
Supply Current vs Temperature
(V
CC
= 3V)
100.10
I
DACOUT
Full Scale vs V
CC
,
V
DACOUT
= 1.1V
T
A
= 25°C
430
420
410
100.00
99.95
400
390
–50
99.90
2.5
6.5
–25
0
25
50
TEMPERATURE (°C)
75
100
1840 G02
3.5
4.5
V
CC
(V)
5.5
6.5
1840 G03
100.10
100.05
100.00
I
DACOUT
FS vs V
DACOUT
at V
CC
= 3V
100.5
I
DACOUT
FS vs V
DACOUT
at V
CC
= 5V
T
A
= 25°C
100.3
100.1
99.9
99.7
99.5
99.3
99.1
T
A
= 25°C
5
6
1840 G04
1.5
2.5
V
DACOUT
(V)
3.5
4.5
1840 G05
0
1
2
3
4
V
DACOUT
(V)
5
6
1840 G06
DAC Zero Scale Error at V
CC
= 3V,
V
DACOUT
= 1.1V
0.2
DAC DNL vs Code at V
CC
= 3V
T
A
= 25°C
0.1
5
0
–0.1
1000
1840 G07
0
–50 –25
–0.2
50
25
75
0
TEMPERATURE (°C)
100
125
1
CODE
255
1840 G09
1840 G08
1840f
LTC1840
TYPICAL PERFOR A CE CHARACTERISTICS
DAC INL at V
CC
= 3V
0.4
T
A
= 25°C
0.3
BLASTB THRESHOLD (V)
BEST FIT INL (LSB)
0.2
0.1
0
–0.1
–0.2
0
CODE
PI FU CTIO S
SCL (Pin 1):
Serial Clock Input. The 2-wire bus master
device clocks this pin at a frequency between 0kHz and
100kHz to enable serial bus communications. Data at the
SDA pin is shifted in or out on rising SCL edges. SCL has
a logic threshold of 1V and an external pull-up resistor or
current source is normally required.
SDA (Pin 2):
Serial Data Input. This is a bidirectional data
pin which normally has an external pull-up resistor or
current source and can be pulled down by the open drain
device on the LTC1840 or by external devices. The master
controls SDA during addressing, the writing of data, and
read acknowledgment, while the LTC1840 controls SDA
when data is being read back and during write acknowl-
edgment. SDA data is shifted in or out on rising SCL edges.
SDA has a logic threshold of 1V.
A1 (Pin 3):
Three State Address Programming Input. This
pin can cause three different logic states internally, de-
pending upon whether it is pulled to supply, pulled to
ground, or not connected (NC). Combined with the A0 pin,
this provides for nine different possible two-wire bus
addresses for the LTC1840 (see Table 1).
A0 (Pin 4):
Three State Address Programming Input. See
A1.
FAULT (Pin 5):
Fault Indicator Pull-Down Output. This pin
has an open drain pull-down that is used to signal various
fault conditions on the LTC1840. An external 10k pull-up
is recommended.
GPIO1, GPIO2, GPIO3, GPIO4 (Pins 6, 7, 9, 10):
General
Purpose Inputs/Outputs. These pins can be used as digital
inputs with CMOS logic thresholds or digital outputs/LED
drivers with open drain pull-downs that can be pro-
grammed to blink. GPIO pins can be programmed to
produce faults due to changes in their logic states, and
these faults can only be cleared by software or powering
the LTC1840 down. All GPIOs default to nonfaulting logic
inputs upon power-up and their functionality is changed
through the serial interface.
GND (Pin 8):
Ground. Connect to analog ground plane.
TACHA (Pin 11):
Tachometer Input A. This pin is a digital
input that is designed to interface to the tachometer output
from a 3-wire fan. Internal logic counts between rising
TACHA edges at serially programmable frequencies of
25kHz, 12.5kHz, 6.25kHz or 3.125kHz and the most re-
cently completed count is stored in a register accessible
through the serial interface. The maximum count is 255
and the LTC1840 is programmable to produce faults when
a count exceeds this number. This pin has CMOS thresh-
olds and the default conditions are to count at 3.125kHz
and to not produce faults.
TACHB (Pin 12):
Tachometer Input B. See TACHA
1840f
U W
BLAST Falling Threshold
at V
CC
= 3V
1.011
1.010
1.009
1.008
1.007
1.006
1.005
1.004
1.003
255
1840 G10
1.002
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
1840 G11
U
U
U
5
FPGA/CPLD
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