DATA SHEET
SKY12347-362LF: DC-3.0 GHz Six-Bit Digital Attenuator with
Serial or Parallel Driver (0.5 dB LSB)
Applications
•
Cellular, 3G/4G, WiMAX, and LTE Infrastructures
Features
•
Broadband operation: DC
to
3.0 GHz
•
Attenuation: 31.5 dB with 0.5 dB LSB
•
TTL/CMOS-compatible serial, parallel, or latched parallel control
interface
•
Single supply voltage: +3.3 or +5 V
•
Small, QFN
(24-pin,
4 x 4 mm) package (MSL1, 260
°C
per
JEDEC J-STD-020)
Figure 1. SKY12347-362LF Block Diagram
Description
The SKY12347-362LF is a GaAs pHEMT six-bit broadband digital
attenuator with a 0.5 dB Least Significant Bit (LSB). A Transistor-
to-Transistor
Logic (TTL)/CMOS-compatible, dual-mode serial or
parallel interface controller is integrated into the device.
The attenuator features low insertion loss, excellent attenuation
accuracy, a 31.5 dB attenuation range, and high linearity
performance. The SKY12347-362LF is an ideal choice for a wide
variety of cellular 3G and 4G infrastructure applications.
Attenuation is controlled by a Serial Peripheral Interface (SPI).
Depending on the SPI sequence applied to the
SDI
pin, the
attenuation state between the RF1 and RF2 pins can vary between
a low insertion loss state or up to 31.5 dB. The D0 through
D5
DC
control pins determine the attenuation state if parallel mode is
enabled.
The device is provided in a 4 x 4 mm, 24-pin Quad Flat No-Lead
(QFN) package. A functional block diagram is shown in Figure 1.
The pin configuration and package are shown in Figure 2. Signal
pin assignments and functional pin descriptions are provided in
Table 1.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
201371B • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • April 7, 2011
1
DATA SHEET • SKY12347-362LF SIX-BIT DIGITAL ATTENUATOR
Figure 2. SKY12347-362LF Pinout – 24-Pin QFN
(Top View)
Table 1. SKY12347-362LF Signal Descriptions
Pin #
1
2
3
4
P/S
CLK
SDI
LE
Name
Description
Selects serial or parallel operation. Logic
low
enables parallel mode.
Serial clock input
Serial data input
On rising edge of pulse, shifts six most
recent clocked-in bits to set attenuation
state. In parallel mode, if latch enable is
logic high, changes to pins 19
to
24 occur
directly. If latch enable is logic low, the
attenuator does not change states until the
signal is raised.
Ground
RF input/output to digital attenuator.
No connection. Can be grounded without
affecting performance.
No connection. Can be grounded without
affecting performance.
No connection. Can be grounded without
affecting performance.
No connection. Can be grounded without
affecting performance.
No connection. Can be grounded without
affecting performance.
No connection. Can be grounded without
affecting performance.
Pin #
13
14
15
16
RF2
GND
SDO
PUP2
Name
Description
RF input/output to digital attenuator.
Ground
Serial data output
Sets device power-up attenuation state. See
Table 7.
5
6
7
8
9
10
11
12
GND
RF1
NC_GND
NC_GND
NC_GND
NC_GND
NC_GND
NC_GND
17
18
19
20
21
22
23
24
PUP1
VDD
D5
D4
D3
D2
D1
D0
Sets device power-up attenuation state. See
Table 7.
DC power supply
TTL/CMOS DC control pin for parallel mode
operation. D5
is MSB.
TTL/CMOS DC control pin for parallel mode
operation
TTL/CMOS DC control pin for parallel mode
operation
TTL/CMOS DC control pin for parallel mode
operation
TTL/CMOS DC control pin for parallel mode
operation
TTL/CMOS DC control pin for parallel mode
operation. D0 is LSB.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
2
April 7, 2011 • Skyworks Proprietary Information • Products and Product
Information
are Subject to Change Without Notice • 201371B
DATA SHEET • SKY12347-362LF SIX-BIT DIGITAL ATTENUATOR
Functional Description
The SKY12347-362LF is a six bit digital attenuator comprised of a
GaAs attenuator and a silicon CMOS driver. The attenuation
setting is controlled by an SPI. Attenuation is set by a stream of
data that is clocked into the shift registers of the silicon chip by
the clock signal. To set the attenuation state, a latch signal is sent
to the appropriate pin to send the correct bias voltages to the
GaAs attenuator.
More than one attenuator can be cascaded together and the data
may be passed through one device to the other using the SDO
signal (pin 15). The DC bias voltage to the silicon CMOS chip is
applied to pin 18 (VDD).
Power-Up/Power-Down Timing
Serial input data (SDI pin) is shifted into the register on the rising
edge of the clock (CLK pin), Least Significant Bit (LSB) first. The
attenuator changes states on the rising edge of the latch enable
(LE pin) signal, according to the most recent six bits of shifted data
accepted since the previous falling edge of the latch enable signal.
The serial data output is the serial input data delayed by six
clock
cycles.
Refer to the timing diagram in Figure 3 and timing parameter
specifications in Table 2. Table 3 shows the transition states
based on the LE and CLK signals.
Power-up sequence is as follows:
0. Connect ground
1. Apply V
DD
2. Set all inputs (CLK,
SDI,
LE)
The power-down sequence is the reverse of above.
Figure 4 shows an example of how to set the attenuator to the
0.5 dB state. The progression of the bit states vs the clock signal
is shown. The timing diagram shows that when the latch enable
signal goes high, the voltages D0
to D5
set the attenuator to the
0.5 dB state.
Electrical and Mechanical Specifications
The absolute maximum ratings of the SKY12347-362LF are
provided in Table 4. Electrical specifications are provided in
Tables
5
and 6.
Typical performance characteristics of the SKY12347-362LF are
illustrated in Figures
5
through 11.
The state of the SKY12347-362LF is determined by the logic
provided in Table 7.
Figure 3. Power-Up/Power-Down Timing
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
201371B • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • April 7, 2011
3
DATA SHEET • SKY12347-362LF SIX-BIT DIGITAL ATTENUATOR
Table 2. Power-Up/Power-Down Timing Parameters
Parameter
Serial input setup time
Hold time from serial input to shift clock
Setup time from shift clock to latch enable
Propagation delay, latch enable to C0.5
through C8
Setup time from reset to shift clock
Clock frequency
Symbol
ts
th
tlsup
tpd
–
f
CLK
20
30
40
30
50
10
V
DD
= 5 V
Minimum
Typical
5
5
100
70
Maximum
Minimum
V
DD
= 3.3 V
Typical
5
5
Maximum
Units
ns
ns
ns
ns
ns
MHz
Table 3. Transition State Logic
LE (Pin 4)
X
X
CLK (Pin 2)
Shift register clocked
Contents of shift register transferred to digital attenuator
Function
Figure 4. Example for Setting 0.5 dB State
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
4
April 7, 2011 • Skyworks Proprietary Information • Products and Product
Information
are Subject to Change Without Notice • 201371B
DATA SHEET • SKY12347-362LF SIX-BIT DIGITAL ATTENUATOR
Table 4. SKY12347-362LF Absolute Maximum Ratings
Parameter
Supply voltage
Control voltage
RF input power
Operating temperature
Storage temperature
Note:
Symbol
V
DD
V
CTL
P
IN
T
OP
T
STG
Minimum
3.3
0
–40
–40
Maximum
6.0
V
DD
+30
+85
+125
Units
V
V
dBm
°C
°C
Exposure to maximum rating conditions for extended periods may reduce device reliability. There is no damage to device with only one parameter set at the limit and all other
parameters set at or below their nominal value. Exceeding any of the limits listed here may result in permanent damage to the device.
CAUTION:
Although this device is designed to be as robust as possible, Electrostatic Discharge (ESD) can damage this device. This device
must be protected at all times from ESD. Static charges may easily produce potentials of several kilovolts on the human body
or equipment, which can discharge without detection. Industry-standard ESD precautions should be used at all times.
Table 5. SKY12347-362LF Electrical Specifications (Note 1) (1 of 2)
(V
DD
= 5 V, V
CTL
= 5 V, T
OP
= +25
°C,
P
IN
= 0 dBm, Characteristic Impedance [Z
O
] = 50
Ω,
, Unless Otherwise Noted)
Parameter
RF Specifications
Insertion loss
Attenuation range
Return loss
Attenuation accuracy
RL
IL
DC
to
0.8 GHz
0.8
to
3.0 GHz
DC to 3.0 GHz
DC to 3.0 GHz
All attenuation states
DC to 0.8 GHz
0.8 to 3.0 GHz
0.1 dB Input Compression Point
3
rd
Order Input Intercept Point
IP0.1dB
IIP3
DC to 3.0 GHz
DC to 3.0 GHz,
P
IN
= +10 dBm/tone,
ΔF
= 1 MHz
±(0.1 + 5% of attenuation setting max)
±(0.3 + 3% of attenuation setting max)
+30
+50
dB
dB
dBm
dBm
0.5
15
1.2
2.0
1.3
2.2
31.5
dB
dB
dB
dB
Symbol
Test Condition
Min
Typical
Max
Units
DC Specifications
Control voltage:
Low
High
Supply voltage
Supply current
V
CTL
0
3.0
V
DD
I
DD
3.3
5.0
100
0.8
V
DD
5.5
V
V
V
μA
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
201371B • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • April 7, 2011
5
电机控制
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
