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SN54HCT646, SN74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS178C – MARCH 1984 – REVISED MARCH 2003
D
D
D
D
D
D
Operating Voltage Range of 4.5 V to 5.5 V
Low Power Consumption, 80-µA Max I
CC
Typical t
pd
= 12 ns
±6-mA
Output Drive at 5 V
Low Input Current of 1
µA
Max
Inputs Are TTL-Voltage Compatible
SN54HCT646 . . . JT OR W PACKAGE
SN74HCT646 . . . DW OR NT PACKAGE
(TOP VIEW)
D
D
D
D
Independent Registers for A and B Buses
Multiplexed Real-Time and Stored Data
True Data Paths
High-Current 3-State Outputs Can Drive Up
To 15 LSTTL Loads
SN54HCT646 . . . FK PACKAGE
(TOP VIEW)
A7
A8
GND
NC
B8
CLKAB
SAB
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
CLKBA
SBA
OE
B1
B2
B3
B4
B5
B6
B7
B8
A1
A2
A3
NC
A4
A5
A6
DIR
SAB
CLKAB
NC
V
CC
CLKBA
SBA
4
5
6
7
8
9
10
11
3
2 1 28 27 26
25
24
23
22
21
20
19
12 13 14 15 16 17 18
OE
B1
B2
NC
B3
B4
B5
NC – No internal connection
description/ordering information
The ’HCT646 devices consist of bus-transceiver circuits with 3-state outputs, D-type flip-flops, and control
circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers.
Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB
or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed
with the ’HCT646 devices.
Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver
mode, data present at the high-impedance port can be stored in either or both registers.
ORDERING INFORMATION
TA
PDIP – NT
–40°C to 85°C
SOIC – DW
CDIP – JT
–55°C to 125°C
CFP – W
LCCC – FK
PACKAGE†
Tube
Tube
Tape and reel
Tube
Tube
Tube
ORDERABLE
PART NUMBER
SN74HCT646NT
SN74HCT646DW
SN74HCT646DWR
SNJ54HCT646JT
SNJ54HCT646W
SNJ54HCT646FK
TOP-SIDE
MARKING
SN74HCT646NT
HCT646
SNJ54HCT646JT
SNJ54HCT646W
SNJ54HCT646FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2003, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
•
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B7
B6
1
SN54HCT646, SN74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS178C – MARCH 1984 – REVISED MARCH 2003
description/ordering information (continued)
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR
determines which bus receives data when OE is active (low). In the isolation mode (OE high), A data can be
stored in one register and /or B data can be stored in the other register.
When an output function is disabled, the input function still is enabled and can be used to store data. Only one
of the two buses, A or B, can be driven at a time.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
FUNCTION TABLE
INPUTS
OE
X
X
H
H
L
L
L
L
DIR
X
X
X
X
L
L
H
H
CLKAB
↑
X
↑
H or L
X
X
X
H or L
CLKBA
X
↑
↑
H or L
X
H or L
X
X
SAB
X
X
X
X
X
X
L
H
SBA
X
X
X
X
L
H
X
X
A1– A8
Input
Unspecified†
Input
Input disabled
Output
Output
Input
Input
DATA I/O
B1– B8
Unspecified†
Input
Input
Input disabled
Input
Input
Output
Output
OPERATION OR FUNCTION
Store A, B unspecified†
Store B, A unspecified†
Store A and B data
Isolation, hold storage
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B bus
Stored A data to B bus
† The data-output functions can be enabled or disabled by various signals at OE and DIR. Data-input functions always are enabled; i.e., data at
the bus terminals is stored on every low-to-high transition of the clock inputs.
2
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SN54HCT646, SN74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS178C – MARCH 1984 – REVISED MARCH 2003
BUS B
21
OE
L
3
DIR
L
1
23
CLKAB CLKBA
X
X
2
SAB
X
22
SBA
L
21
OE
L
3
DIR
H
1
CLKAB
X
23
CLKBA
X
2
SAB
L
BUS B
22
SBA
X
REAL-TIME TRANSFER
BUS A TO BUS B
1
CLKAB
X
H or L
23
CLKBA
H or L
X
2
SAB
X
H
BUS B
22
SBA
H
X
TRANSFER STORED DATA
TO A AND/OR B
BUS A
REAL-TIME TRANSFER
BUS B TO BUS A
BUS B
BUS A
21
OE
X
X
H
3
DIR
X
X
X
1
23
CLKAB CLKBA
X
↑
X
↑
↑
↑
STORAGE FROM
A, B, OR A AND B
2
SAB
X
X
X
22
SBA
X
X
X
21
OE
L
L
Pin numbers shown are for the DW, JT, NT, and W packages.
Figure 1. Bus-Management Functions
POST OFFICE BOX 655303
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BUS A
3
DIR
L
H
BUS A
3
SN54HCT646, SN74HCT646
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS178C – MARCH 1984 – REVISED MARCH 2003
logic diagram (positive logic)
OE
21
DIR
CLKBA
SBA
CLKAB
SAB
3
23
22
1
2
One of Eight Channels
1D
C1
A1
4
20
1D
C1
B1
To Seven Other Channels
Pin numbers shown are for the DW, JT, NT, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±35
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±70
mA
Package thermal impedance,
θ
JA
(see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
(see Note 3): NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-3.
4
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•
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