Datasheet
Low Duty LCD Segment Driver
for Automotive Application
BU91797xxx-M Series
General Description
BU91797MUF-M and BU91797FUV-M are a 1/4 duty
general-purpose LCD driver that can be used for
automotive applications and can drive up to 144 LCD
Segments.
It can support operating temperature of up to +105°C and
qualified for AEC-Q100 Grade2, as required for
automotive applications.
Wettable flank QFN package is suitable for small
footprint
applications
and
provides
significant
advantages in inspectability and solder joint reliability.
MAX 144 Segments (SEG36×COM4)
Key Specifications
■
■
■
■
■
■
Supply Voltage Range:
+2.5V to +6.0V
Operating Temperature Range:
-40°C to +105°C
Max Segments:
144Segments
Display Duty:
1/4
Bias:
1/3
Interface:
2wire Serial Interface
Special Characteristics
■
■
ESD(HBM):
Latch-up Current:
±2000V
±100mA
W (Typ) x D (Typ) x H (Max)
Features
AEC-Q100 Qualified
(Note)
Integrated RAM for Display Data (DDRAM):
36 x 4 bit (Max 144 Segment)
LCD Drive Output:
4 Common Output, Max 36 Segment Output
Integrated Buffer AMP for LCD Driving
Integrated Oscillator Circuit
No External Components
Low Power Consumption Design
Package
(Note) Grade 2
Applications
etc.
Instrument Clusters
Climate Controls
Car Audios / Radios
Metering
White Goods
Healthcare Products
Battery Operated Applications
VQFN48FV7070
7.0mm x 7.0mm x 1.0mm
TSSOP-C48V
12.5mm x 8.1mm x 1.0mm
Typical Application Circuit
VDD
C > 0.1μF
VDD
VLCD
COM0
COM1
COM2
COM3
Controller
SDA
SCL
SEG0
SEG1
・
・
・
・
・
・
・
SEG35
Segment
LCD
・
・
・
・
・
・
・
Insert Capacitors
between VDD and VSS
OSCIN
TEST1
TEST2
VSS
Internal Clock Mode
Figure 1. Typical Application Circuit
〇Product
structure : Silicon monolithic integrated circuit
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© 2015 ROHM Co., Ltd. All rights reserved.
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〇This
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BU91797xxx-M Series
MAX 144 segments (SEG36×COM4)
Datasheet
Block Diagram / Pin Configuration / Pin Description
BU91797MUF-M
COM 0
……
COM3
VDD
LCD voltage generator
Common
Driver
SEG0
……
SEG35
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
26
SEG25
25
COM0
36
35
34
33
32
31
30
29
28
27
Segment
Driver
COM1
＋
－
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
LCD
BIAS
SELECTOR
Common
Counter
Blink Timing
Generator
DDRAM
COM2
COM3
VLCD
＋
－
VDD
VSS
EXT-PAD
19
18
17
16
15
14
13
VLCD
TEST1
OSCIN
SCL
OSCIN
OSCILLATOR
Power On Reset
Command
Register
Command
Data Decoder
SDA
TEST2
SEG0
Serial Interface
10
11
SEG11
SEG10
VSS
TEST1
TEST2
SDA
SCL
Figure 2. Block Diagram
Figure 3. Pin Configuration (TOP VIEW)
Table 1. Pin Description
Pin Name
TEST1
TEST2
Pin No.
43
47
I/O
I
I
Function
Test input (ROHM use only)
Must be connected to VSS
POR enable setting
VDD: POR disenable
(Note
1)
VSS: POR enable
External clock input
External clock and Internal clock can be selected by command
Must be connected to VSS when using internal oscillator
Serial data in-out terminal
Serial clock terminal
GND
Power supply
Power supply for LCD driving
SEGMENT output for LCD driving
COMMON output for LCD driving
Substrate
Handling
when unused
VSS
VSS
OSCIN
SDA
SCL
VSS
VDD
VLCD
SEG0 to SEG35
COM0 to COM3
EXT-PAD
44
46
45
42
41
40
1 to 35,
48
36 to 39
(Note
2)
I
I/O
I
-
-
-
O
O
-
SEG12
IF FILTER
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
12
1
2
3
4
5
6
7
8
9
VSS
-
-
-
-
-
OPEN
OPEN
OPEN/VSS
(Note
1)
This function is guaranteed by design, not tested in production process. Software Reset is necessary to initialize IC in case of TEST2=VDD.
(Note
2)
To radiate heat, Contact a board with the EXT-PAD which is located at the bottom side of VQFN48FV7070 package.
Supply VSS level or Open state as the input condition for this PAD.
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BU91797xxx-M Series
MAX 144 segments (SEG36×COM4)
Datasheet
Block Diagram / Pin Configuration / Pin Description – continued
BU91797FUV-M
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
COM 0
……
COM3
VDD
LCD voltage generator
SEG0
……
SEG35
SEG32
SEG33
SEG34
Common
Driver
Segment
Driver
SEG35
COM0
COM1
＋
－
LCD
BIAS
SELECTOR
Common
Counter
Blink Timing
Generator
DDRAM
COM2
COM3
VLCD
VDD
VSS
TEST1
＋
－
VLCD
OSCIN
SCL
SDA
OSCIN
OSCILLATOR
Power On Reset
Command
Register
Command
Data Decoder
TEST2
SEG0
Serial Interface
SEG1
SEG2
IF FILTER
VSS
SEG3
SEG4
SEG5
TEST1
TEST2
SDA
SCL
SEG6
Figure 4. Block Diagram
Figure 5. Pin Configuration (TOP VIEW)
Table 2. Pin Description
Pin Name
TEST1
TEST2
Pin No.
13
17
I/O
I
I
Test input (ROHM use only)
Must be connected to VSS
POR enable setting
VDD: POR disenable
(Note)
VSS: POR enable
External clock input
External clock and Internal clock can be selected by command
Must be connected to VSS when using internal oscillator
Serial data in-out terminal
Serial clock terminal
GND
Power supply
Power supply for LCD driving
SEGMENT output for LCD driving
COMMON output for LCD driving
Function
Handling
when unused
VSS
VSS
OSCIN
SDA
SCL
VSS
VDD
VLCD
SEG0 to SEG35
COM0 to COM3
14
16
15
12
11
10
18 to 48,
1 to 5
6 to 9
I
I/O
I
-
-
-
O
O
VSS
-
-
-
-
-
OPEN
OPEN
(Note)
This function is guaranteed by design, not tested in production process. Software Reset is necessary to initialize IC in case of TEST2=VDD.
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TSZ02201-0P4P0D3P01040-1-2
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BU91797xxx-M Series
MAX 144 segments (SEG36×COM4)
Datasheet
Absolute Maximum Ratings
(VSS=0V)
Parameter
Maximum Voltage1
Maximum Voltage2
Power Dissipation
Input Voltage Range
Operational Temperature
Range
Storage Temperature Range
Symbol
VDD
VLCD
Pd
V
IN
Topr
Tstg
Ratings
-0.5 to +7.0
-0.5 to VDD
0.93
(Note
1)
0.64
(Note
2)
-0.5 to VDD+0.5
-40 to +105
-55 to +125
Unit
V
V
W
W
V
°C
°C
Power Supply
LCD Drive Voltage
BU91797MUF-M
BU91797FUV-M
Remarks
(Note
1)
Derate by 9.3mW/°C when operating above Ta=+25°C (when mounted in ROHM’s standard board).
(Note
2)
Derate by 6.4mW/°C when operating above Ta=+25°C (when mounted in ROHM’s standard board).
Caution:
Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over
the absolute maximum ratings.
Recommended Operating Conditions
(Ta=-40°C to +105°C, VSS=0V)
Parameter
Power Supply Voltage1
Power Supply Voltage2
Symbol
VDD
VLCD
Ratings
Min
2.5
0
Typ
-
-
Max
6.0
VDD-2.4
Unit
V
V
Power Supply
LCD Drive Voltage, VDD-VLCD
2.4V
Remarks
Electrical Characteristics
DC Characteristics (VDD=2.5V to 6.0V, VLCD=0V, VSS=0V, Ta=-40°C to +105°C, unless otherwise specified)
Limits
Parameter
Symbol
Unit
Conditions
Min
Typ
Max
“H” Level Input Voltage
“L” Level Input Voltage
“H” Level Input Current
“L” Level Input Current
SDA “L” Level Output Voltage
LCD Driver On
Resistance
SEG
COM
V
IH
V
IL
I
IH
I
IL
V
OL_SDA
R
ON
R
ON
VLCD
I
DD1
I
DD2
0.7VDD
VSS
-
-1
0
-
-
0
-
-
-
-
-
-
-
3
3
-
-
12.5
VDD
0.3VDD
1
-
0.4
-
-
VDD-2.4
5
30
V
V
µA
µA
V
kΩ
kΩ
V
µA
µA
SDA, SCL, OSCIN
SDA, SCL, OSCIN
SDA, SCL, OSCIN
(Note
3)
, TEST2
SDA, SCL, OSCIN, TEST2
Iload = 3mA
Iload=±10µA
VDD-VLCD2.4V
Display off, Oscillation off
VDD=3.3V, VLCD=0V, Ta=+25°C
Power save mode1, FR=71Hz
1/3 bias, Frame inverse
VLCD Supply Voltage
Standby Current
Power Consumption
(Note
3)
For external clock mode only.
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TSZ02201-0P4P0D3P01040-1-2
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BU91797xxx-M Series
MAX 144 segments (SEG36×COM4)
Datasheet
Electrical Characteristics – continued
Oscillation Characteristics (VDD=2.5V to 6.0V, VLCD=0V, VSS=0V, Ta=-40°C to +105°C, unless otherwise specified)
Limits
Parameter
Symbol
Unit
Conditions
Min
Typ
Max
FR = 80Hz setting,
Frame Frequency1
f
CLK1
56
80
112
Hz
VDD=2.5V to 6.0V, Ta=-40°C to +105°C
FR = 80Hz setting, VDD=3.3V,
Frame Frequency2
f
CLK2
70
80
90
Hz
Ta=+25°C
FR = 80Hz setting, VDD=5.0V,
Frame Frequency3
f
CLK3
77.5
87.5
97.5
Hz
Ta=+25°C
FR = 80Hz setting, VDD=5.0V,
Frame Frequency4
f
CLK4
67.5
87.5
108
Hz
Ta=-40°C to +105°C
External Clock Rise Time
tr
-
-
0.3
µs
External Clock Fall Time
External Frequency
External Clock Duty
tf
f
EXCLK
t
DTY
-
15
30
-
-
50
/ 512
/ 576
/ 648
/ 768
0.3
300
70
µs
kHz
%
External clock mode (OSCIN)
(Note)
(Note) <Frame frequency calculation at external clock mode>
DISCTL 80HZ setting: Frame frequency [Hz] = external clock [Hz]
DISCTL 71HZ setting: Frame frequency [Hz] = external clock [Hz]
DISCTL 64HZ setting: Frame frequency [Hz] = external clock [Hz]
DISCTL 53HZ setting: Frame frequency [Hz] = external clock [Hz]
[Reference Data]
110
100
Frame Frequency [Hz]
VDD = 6.0V
VDD = 5.0V
90
VDD = 3.3V
80
70
60
50
-40 -20
0
20
VDD = 2.7V
40
60
80 100
Temperature [°C]
Figure 6. Frame Frequency Typical Temperature Characteristics
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