NCP1340
High-Voltage,
Quasi-Resonant, Controller
Featuring Valley Lock-Out
Switching
The NCP1340 is a highly integrated quasi−resonant flyback
controller suitable for designing high−performance off−line power
converters. With an integrated active X2 capacitor discharge feature,
the NCP1340 can enable no−load power consumption below 30 mW.
The NCP1340 features a proprietary valley−lockout circuitry,
ensuring stable valley switching. This system works down to the 6
th
valley and transitions to frequency foldback mode to reduce switching
losses. As the load decreases further, the NCP1340 enters quiet−skip
mode to manage the power delivery while minimizing acoustic noise.
To help ensure converter ruggedness, the NCP1340 implements
several key protective features such as internal brownout detection, a
non−dissipative Over Power Protection (OPP) for constant maximum
output power regardless of input voltage, a latched overvoltage and
NTC−ready overtemperature protection through a dedicated pin, and
line removal detection to safely discharge the X2 capacitors when the
ac line is removed.
If transient load capability is desired, the NCP1341 offers the same
performance and features with the addition of power excursion mode
(PEM).
Features
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8
1
SOIC−8 NB
D SUFFIX
CASE 751
9
1
SOIC−9 NB
D SUFFIX
CASE 751BP
MARKING DIAGRAM
9
1340xz
ALYW
G
1
1340xz
x
z
A
L
Y
W
G
= Specific Device Code
= A or B
= 1, 2, 3, 4, 5, 6, or 7
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Integrated High−Voltage Startup Circuit with Brownout Detection
Integrated X2 Capacitor Discharge Capability
Wide V
CC
Range from 9 V to 28 V
28 V V
CC
Overvoltage Protection
Abnormal Overcurrent Fault Protection for Winding Short Circuit or
Saturation Detection
Internal Temperature Shutdown
Valley Switching Operation with Valley−Lockout for Noise−Free
Operation
Frequency Foldback with 25 kHz Minimum Frequency Clamp for
Increased Efficiency at Light Loads
Skip Mode with Quiet−Skip Technology for Highest Performance
During Light Loads
Minimized Current Consumption for No Load Power Below 30 mW
Frequency Jittering for Reduced EMI Signature
Latching or Auto−Recovery Timer−Based Overload Protection
Adjustable Overpower Protection (OPP)
Fixed or Adjustable Maximum Frequency Clamp
Fault Pin for Severe Fault Conditions, NTC Compatible for OTP
4 ms Soft−Start Timer
PIN CONNECTIONS
1
Fault
FB
ZCD/OPP
CS
1
Fault
FMAX
FB
ZCD/OPP
CS
(Top Views)
HV
VCC
DRV
GND
HV
VCC
DRV
GND
ORDERING INFORMATION
See detailed ordering and shipping information n on page 3
of this data sheet.
©
Semiconductor Components Industries, LLC, 2017
1
June, 2018 − Rev. 10
Publication Order Number:
NCP1340/D
NCP1340
TYPICAL APPLICATION SCHEMATIC
Figure 1. NCP1340 8−Pin Typical Application Circuit
Figure 2. NCP1340 9−Pin Typical Application Circuit
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2
NCP1340
Table 1. ORDERING INFORMATION TABLE
Orderable Part Number
NCP1340A3D1R2G
NCP1340B1DR2G
NCP1340B3D1R2G
NCP1340B4D1R2G
NCP1340B5D1R2G
NCP1340A6DR2G
NCP1340B6DR2G
NCP1340B7D1R2G
Device Marking
1340A3
1340B1
1340B3
1340B4
1340B5
1340A6
1340B6
1340B7
Package
SOIC−9
SOIC−8
SOIC−9
SOIC−9
SOIC−9
SOIC−8
SOIC−8
SOIC−9
Shipping
†
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Table 2. DEVICE DIFFERENTIATION TABLE
Ordering Code
NCP1340A3D1R2G
NCP1340B1DR2G
NCP1340B3D1R2G
NCP1340B4D1R2G
NCP1340B5D1R2G
NCP1340A6DR2G
NCP1340B6DR2G
NCP1340B7D1R2G
Pins
9
8
9
9
9
8
8
9
Fault
Pin
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
FMAX
Pin
Yes
No
Yes
Yes
Yes
No
No
Yes
X2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
OTP/Overload
Protection
Latched
Auto−Restart
Auto−Restart
Auto−Restart
Auto−Restart
Latched
Auto−Restart
Auto−Restart
Frequency
Clamp
Adjustable
None
Adjustable
Adjustable
Adjustable
None
None
Adjustable
R
FB
Pullup
400 kW
400 kW
400 kW
20 kW
20 kW
20 kW
20 kW
20 kW
V
CC
OVP
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
I
FB
Pullup
100
mA
100
mA
100
mA
None
None
None
None
None
Jitter
1.3kHz
1.3kHz
1.3kHz
1.3kHz
None
None
None
None
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NCP1340
FUNCTIONAL BLOCK DIAGRAM
Figure 3. NCP1340 Block Diagram
Table 3. PIN FUNCTIONAL DESCRIPTION
8−Pin
1
−
2
3
4
5
6
7
9−Pin
1
2
3
4
5
6
7
8
Pin Name
Fault
FMAX
FB
ZCD/OPP
CS
GND
DRV
VCC
Function
The controller enters fault mode if the voltage on this pin is pulled above or below the fault
thresholds. A precise pull up current source allows direct interface with an NTC thermistor.
A resistor to ground sets the value for the maximum switching frequency clamp. If this pin is
pulled above 4 V, the maximum frequency clamp is disabled.
Feedback input for the QR Flyback controller. Allows direct connection to an optocoupler.
A resistor divider from the auxiliary winding to this pin provides input to the demagnetization de-
tection comparator and sets the OPP compensation level.
Input to the cycle−by−cycle current limit comparator.
Ground reference.
This is the drive pin of the circuit. The DRV high−current capability (−0.5 /+0.8 A) makes it suit-
able to effectively drive high gate charge power MOSFETs.
This pin is the positive supply of the IC. The circuit starts to operate when V
CC
exceeds 17 V and
turns off when V
CC
goes below 9 V (typical values). After start−up, the operating range is 9 V up
to 28 V.
Removed for creepage distance.
This pin is the input for the high voltage startup and brownout detection circuits. It also contains
the line removal detection circuit to safely discharge the X2 capacitors when the line is removed.
−
8
9
10
N/C
HV
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NCP1340
Table 4. MAXIMUM RATINGS
Rating
High Voltage Startup Circuit Input Voltage
High Voltage Startup Circuit Input Current
Supply Input Voltage
Supply Input Current (Note 1)
Supply Input Voltage Slew Rate
Fault Input Voltage
Fault Input Current
Zero Current Detection and OPP Input Voltage
Zero Current Detection and OPP Input Current
Maximum Input Voltage (Other Pins)
Maximum Input Current (Other Pins)
Driver Maximum Voltage (Note 2)
Driver Maximum Current
Operating Junction Temperature
Storage Temperature Range
Power Dissipation (T
A
= 25°C, 1 oz. Cu, 42 mm
2
Copper Clad Printed Circuit)
DR2G Suffix, SOIC−8
D1R2G Suffix, SOIC−9
Thermal Resistance (T
A
= 25°C, 1 oz. Cu, 42 mm
2
Copper Clad Printed Circuit)
DR2G Suffix, SOIC−8
D1R2G Suffix, SOIC−9
ESD Capability
Human Body Model per JEDEC Standard JESD22−A114F (All pins except HV)
Human Body Model per JEDEC Standard JESD22−A114F (HV Pin)
Charge Device Model per JEDEC Standard JESD22−C101F
Latch−Up Protection per JEDEC Standard JESD78E
Symbol
V
HV(MAX)
I
HV(MAX)
V
CC(MAX)
I
CC(MAX)
dV
CC
/dt
V
Fault(MAX)
I
Fault(MAX)
V
ZCD(MAX)
I
ZCD(MAX)
V
MAX
I
MAX
V
DRV
I
DRV(SRC)
I
DRV(SNK)
T
J
T
STG
P
D(MAX)
450
330
R
qJA
°C/W
225
300
2000
800
1000
±100
V
V
V
mA
Value
−0.3 to 700
20
−0.3 to 30
30
1
−0.3 to V
CC
+ 0.7 V
10
−0.3 to V
CC
+ 0.7 V
−2/+5
−0.3 to 5.5
10
−0.3 to V
DRV(high)
500
800
−40 to 125
–60 to 150
Unit
V
mA
V
mA
V/ms
V
mA
V
mA
V
mA
V
mA
°C
°C
mW
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The V
CC
pin is rated to handle the full transient current of the DRV pin.
2. Maximum driver voltage is limited by the driver clamp voltage, V
DRV(high)
, when V
CC
exceeds the driver clamp voltage. Otherwise, the
maximum driver voltage is V
CC
.
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