FEDR45V
V100A-01
Iss
sue Date: Sep. 4, 2017
MR
R45V1
100A
1M Bit(
(131,072-Wor
×
8-Bit) FeR
rd
RAM (Ferroel
lectric Random Access Mem
m
mory)
SPI
GENER
RAL DESCR
RIPTION
The MR4
45V100A is a nonvolatile 128Kword x 8
1
8-bit ferroelec
ctric random access memor (FeRAM) developed
a
ry
in the fe
erroelectric pr
rocess and sil
licon-gate CM
MOS technolo
ogy. The MR
R45V100A is accessed using Serial
s
Periphera Interface. U
al
Unlike SRAMs this device, whose cells are nonvolatile eliminates b
s,
a
e,
battery backup required
p
to hold d
data. This dev
vice has no mechanisms of erasing and programming memory cel and block such as
m
f
g
ells
ks,
those use for various EEPROMs. Therefore, th e write cycle time can be equal to the r
ed
s
read cycle tim and the
me
power co
onsumption du
uring a write can be reduced significantly
c
d
y.
The MR4
45V100A can be used in va
arious applicat
tions, because the device is guaranteed fo the write/re
e
or
ead
12
tolerance of 10 cycles per bit and the rewrite cou can be ext
t
unt
tended signific
cantly.
FEATUR
RES
•
•
•
•
•
•
•
131,072
2-word
×
8-bit configuration (Serial Perip
t
pheral Interface: SPI)
A single 1.8V to 3.6V
（3.3V
typ.） power supp
V
）
ply
ing
READ cycle) / 40MHz(Exc
cept for READ
D)
Operati frequency:
34MHz(R
12
Read/w
write tolerance
10 cycle
es/bit
Data ret
tention
10 years
Guarant
g
5°C
teed operating temperature range
−40
to 85
Low po
ower consump
ption
Power supply curren (@40MHz)
nt
3.0mA(T
Typ.),
4.5mA(Max.)
Standb mode suppl current
by
ly
10μA(Ty
yp.),
50
0μA(Max.)
Sleep m
mode supply c
current
0.1μA(Ty
yp.),
2μ
μA(Max.)
• Package options:
e
8-p plastic SO (P-SOP8-200-1.27-T2K)
pin
OP
)
8-p plastic DIP (P-DIP8-300-2.54-T6)
pin
P
• RoHS (
(Restriction of hazardous su
f
ubstances) com
mpliant
1/21
FEDR45V100A-01
MR45V100A
PIN CONFIGURATION (Top View)
8-pin plastic SOP / DIP
CS#
SO
WP#
VSS
1
2
3
4
8
7
6
5
VCC
HOLD#
SCK
SI
Note:
Signal names that end with # indicate that the signals are negative-true logic.
MR45V100A
PIN DESCRIPTIONS
Pin Name
CS#
Description
Chip Select (input, negative logic)
Latches an address by low input, activates the FeRAM, and enables read or write
operation. High input goes the device disable state.
Write Protect( input, negative logic )
Write Protect pin controls write-operation to the status-register(BP0,BP1). This pin should
be fixed low or high in write-operations.
HOLD( input, negative logic )
Hold pin is used when the serial-communication suspended without disable the chip
select. When HOLD# is low, the serial-output is in High-Z status and
serial-input/serial-clock are “Don’t Care”. CS# should be low in hold operation.
Serial Clock
Serial Clock is the clock input pin for setting for serial data timing. Inputs are latched on the
rising edge and outputs occur on the falling edge.
Serial input
SI pins are serial input pins for Operation-code, addresses, and data-inputs.
Serial output
SO pins are serial output pins.
Power supply
Apply the specified voltage to V
CC
. Connect V
SS
to ground.
WP#
HOLD#
SCK
SI
SO
V
CC
, V
SS
2/21
FEDR45V100A-01
MR45V100A
SPI MODE (Serial Peripheral Interface)
SPI mode0（CPOL=0, CPHA=0）
CS#
SCK
SI
MSB
LSB
SPI mode3（CPOL=1, CPHA=1）
CS#
SCK
SI
MSB
LSB
STATUS REGISTER
b7
SRWD
0
0
0
BP1
BP0
WEL
b0
WIP
Status Register Write Disable
Block Protect Bits
Write Enable Latch
Write In Progress (Always 0)
Name
WIP
WEL
BP0,BP1
SRWD
Function
Fixed to 0.
Write Enable Latch. This indicates internal WEL condition.
Block Protect: These bits can change protected area.
This is the software protect.
Status Register Write Disable（SRWD）: SRWD controls the effect of the hardware
WP# pin. This device will be in hardware-protect by combination of SRWD and
WP#.
Fixed to 0.
0
3/21
FEDR45V100A-01
MR45V100A
OPERATION-CODE
Operation codes are listed in the table below. If the device receives invalid operation code, the device will be
deselected.
Instruction
Description
Instruction format
WREN
Write Enable
0000 0110
WRDI
Write Disable
0000 0100
RDSR
Read Status Register
0000 0101
WRSR
Write Status Register
0000 0001
READ
Read from Memory Array
0000 0011
WRITE
Write to Memory Array
0000 0010
FSTRD
Fast Read from Memory Array
0000 1011
RDID
Read device ID
1001 1111
SLEEP
Enter Sleep Mode
1011 1001
4/21
FEDR45V100A-01
MR45V100A
COMMANDS
WREN (Write Enable)
It is necessary to set Write Enable Latch（WEL）bit before write-operation (WRITE and WRSR).
WREN command sets WEL bit.
CS#
WP#
SCK
SI
SO
High-Z
Fixed “H”
0
1
2
3
4
5
6
7
WRDI (Write Disable)
WRDI command resets WEL bit.
CS#
WP#
SCK
SI
SO
Fixed “H”
0
1
2
3
4
5
6
7
High-Z
5/21
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