Datasheet
Serial EEPROM Series Standard EEPROM
SPI BUS EEPROM
BR25G512-3
General Description
BR25G512-3 is a 512Kbit serial EEPROM of SPI BUS interface.
Features
High Speed Clock Action up to 10MHz (Max)
Wait Function by HOLDB Terminal
Part or Whole of Memory Arrays Settable as
Read only Memory Area by Program
1.8V to 5.5V Single Power Source Operation Most
Suitable for Battery Use.
UP to 128Byte in Page Write Mode.
For SPI bus interface (CPOL, CPHA) = (0, 0), (1, 1)
Self-timed Programming Cycle
Low Current Consumption
At Write Action (5V) : 0.7mA (Typ)
At Read Action (5V) : 2.4mA (Typ)
At Standby Action (5V) : 0.1µA (Typ)
Address Auto Increment Function at Read Action
Prevention of Write Mistake
Write Prohibition at Power On
Write Prohibition by Command Code (WRDI)
Write Prohibition by WPB Pin
Write Prohibition Block Setting by Status Registers
(BP1, BP0)
Prevention of Write Mistake at Low Voltage
More than 100 years Data Retention.
More than 1 Million Write Cycles.
Bit Format 64K×8
Initial Delivery Data
Memory Array: FFh
Status Register: WPEN, BP1, BP0 : 0
Packages
W(Typ) x D(Typ) x H(Max)
SOP8
5.00mm x 6.20mm x 1.71mm
SOP- J8
4.90mm x 6.00mm x 1.65mm
TSSOP-B8
3.00mm x 6.40mm x 1.20mm
Figure 1.
○Product
structure：Silicon monolithic integrated circuit
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○This
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BR25G512-3
Absolute Maximum Ratings
(Ta=25°C)
Parameter
Supply Voltage
Power Dissipation
Storage Temperature
Operating Temperature
Input Voltage /
Output Voltage
Junction temperature
Electrostatic discharge
voltage
(human body model)
Symbol
V
CC
Pd
Tstg
Topr
‐
Tjmax
V
ESD
Ratings
-0.3 to +6.5
0.45 (SOP8)
0.45 (SOP-J8)
0.33 (TSSOP-B8)
- 65 to +150
- 40 to +85
- 0.3 to Vcc+1.0
150
-4000 to +4000
Unit
V
W
°C
°C
V
°C
V
Remarks
Datasheet
When using at Ta=25°C or higher 4.5mW to be reduced per 1°C.
When using at Ta=25°C or higher 4.5mW to be reduced per 1°C.
When using at Ta=25°C or higher 3.3mW to be reduced per 1°C.
The Max value of Terminal Voltage is not over 6.5V.
When the pulse width is 50ns or less, the Min value of Terminal
Voltage is not under -1.0V.
Junction temperature at the storage condition
Caution:
Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over
the absolute maximum ratings.
Memory Cell Characteristics (Ta=25°C, Vcc=1.8V to 5.5V)
Parameter
Write Cycles
(Note1)
Data Retention
(Note1)
(Note1) Not 100% TESTED
Limits
Min
Typ
1,000,000
-
100
-
Max
-
-
Unit
Times
Years
Recommended Operating Ratings
Parameter
Power Source Voltage
Input Voltage
Symbol
Vcc
V
IN
Ratings
1.8 to 5.5
0 to Vcc
Unit
V
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Electrical Characteristics
(Unless otherwise specified, Ta=-40°C to +85°C, Vcc=1.8V to 5.5V)
Parameter
Input High Voltage1
Input Low Voltage1
Output Low Voltage1
Output Low Voltage2
Output High Voltage1
Output High Voltage2
Input Leakage Current
Output Leakage Current
Supply Current (Write)
I
CC2
I
CC3
Supply Current (Read)
I
CC4
I
CC5
I
CC6
Standby Current
I
SB
－
－
－
－
－
－
－
－
－
－
－
－
2
0.7
1
3
4
1
mA
mA
mA
mA
mA
µA
Symbol
V
IH1
V
IL1
V
OL1
V
OL2
V
OH1
V
OH2
I
LI
I
LO
I
CC1
Min
0.7 x Vcc
-0.3
(Note1)
0
0
Vcc-0.2
Vcc-0.2
-1
-1
－
Limits
Typ
－
－
－
－
－
－
－
－
－
Max
Vcc+1.0
0.3 x Vcc
0.4
0.2
Vcc
Vcc
1
1
1.5
Unit
V
V
V
V
V
V
µA
µA
mA
Conditions
1.8≤Vcc≤5.5V
1.8≤Vcc≤5.5V
I
OL
=3.0mA, 2.5≤Vcc≤5.5V
I
OL
=1.0mA, 1.8≤Vcc<2.5V
I
OH
=-2.0mA, 2.5V≤Vcc≤5.5V
I
OH
=-400µA, 1.8≤Vcc<2.5V
V
IN
=0 to Vcc
V
OUT
=0 to Vcc, CSB=Vcc
Datasheet
Vcc=2.5V, f
SCK
=5MHz, t
E/W
=5ms
Byte Write, Page Write, Write Status Register
Vcc=5.5V, f
SCK
=10MHz, t
E/W
=5ms
Byte Write, Page Write, Write Status Register
Vcc=1.8V, f
SCK
=3MHz, SO=OPEN
Read, Read Status Register
VIH/VIL=0.9Vcc/0.1Vcc
Vcc=2.5V, f
SCK
=5MHz, SO=OPEN
Read, Read Status Register
VIH/VIL=0.9Vcc/0.1Vcc
Vcc=5.5V, f
SCK
=5MHz, SO=OPEN
Read, Read Status Register
VIH/VIL=0.9Vcc/0.1Vcc
Vcc=5.5V, f
SCK
=10MHz, SO=OPEN
Read, Read Status Register
VIH/VIL=0.9Vcc/0.1Vcc
Vcc=5.5V, SO=OPEN
CSB=HOLDB=WPB=Vcc, SCK=SI=Vcc or GND
(Note1) When the pulse width is 50ns or less, it is -1.0V.
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1.8≤Vcc<2.5V 2.5≤Vcc<4.5V 4.5≤Vcc≤5.5V Unit
Min Typ Max Min Typ Max Min Typ Max
0.01 -
3 0.01 -
5 0.01 -
10 MHz
125
-
-
80
-
-
40
-
-
ns
125 -
-
80
-
-
40
-
-
ns
90
-
-
40
-
-
20
-
-
ns
60
-
-
30
-
-
15
-
-
ns
60
-
-
30
-
-
15
-
-
ns
50
-
-
20
-
-
15
-
-
ns
50
-
-
20
-
-
15
-
-
ns
20
-
-
10
-
-
5
-
-
ns
20
-
-
10
-
-
5
-
-
ns
-
-
125
-
-
70
-
-
40
ns
0
-
-
0
-
-
0
-
-
ns
-
-
80
-
-
40
-
-
25
ns
0
-
-
0
-
-
0
-
-
ns
20
-
-
20
-
-
10
-
-
ns
0
-
-
0
-
-
0
-
-
ns
20
-
-
20
-
-
10
-
-
ns
-
-
80
-
-
40
-
-
25
ns
-
-
80
-
-
40
-
-
20
ns
-
-
2
-
-
2
-
-
2
µs
-
-
2
-
-
2
-
-
2
µs
-
-
40
-
-
40
-
-
20
ns
-
-
40
-
-
40
-
-
20
ns
-
-
5
-
-
5
-
-
5
ms
Datasheet
Operating Timing Characteristics (Ta=-40°C to +85°C, unless otherwise specified, load capacity C
L
=30pF)
Parameter
SCK Frequency
SCK High Time
SCK Low Time
CSB High Time
CSB Setup Time
CSB Hold Time
SCK Setup Time
SCK Hold Time
SI Setup Time
SI Hold Time
Data Output Delay Time
Output Hold Time
Output Disable Time
HOLDB Setting Setup Time
HOLDB Setting Hold Time
HOLDB Release Setup Time
HOLDB Release Hold Time
Time from HOLDB to Output High-Z
Time from HOLDB to Output change
SCK Rise Time
(Note1)
SCK Fall Time
(Note1)
OUTPUT Rise Time
(Note1)
OUTPUT Fall Time
(Note1)
Write Time
(Note1) NOT 100% TESTED
Symbol
f
SCK
t
SCKWH
t
SCKWL
t
CS
t
CSS
t
CSH
t
SCKS
t
SCKH
t
DIS
t
DIH
t
PD
t
OH
t
OZ
t
HFS
t
HFH
t
HRS
t
HRH
t
HOZ
t
HPD
t
RC
t
FC
t
RO
t
FO
t
E/W
AC Timing Characteristics Conditions
Parameter
Load Capacity
Input Voltage
Input / Output Judgment Voltage
Symbol
C
L
-
-
Limits
Min
Typ
Max
-
-
30
0.2Vcc/0.8Vcc
0.3Vcc/0.7Vcc
Unit
pF
V
V
Input / Output Capacity
(Ta=25°C, frequency=5MHz)
Parameter
Input Capacity
(Note1)
Output Capacity
(Note1)
(Note1)
Not 100% TESTED.
Symbol
C
IN
C
OUT
Min
－
－
Max
8
8
Unit
pF
Conditions
V
IN
=GND
V
OUT
=GND
Serial Input / Output Timing
tCS
tCSS
tCS
CSB
tSCKS
tSCKWL
tSCKWH
tRC
tFC
CSB
SCK
tCSH tSCKH
SCK
tDIS tDIH
SI
SO
High-Z
SI
SO
tPD
tOH
tRO,tFO
tOZ
High-Z
Figure 2-(a). Input timing
SI is taken into IC inside in sync with data rise edge of
SCK. Input address and data from the most significant bit
MSB
CSB
"H"
"L"
Figure 2-(b). Input / Output timing
SO is output in sync with data fall edge of SCK. Data is
output from the most significant bit MSB.
tHFS
tHFH
tHRS tHRH
SCK
tDIS
SI
n+1
tHOZ
High-Z
tHPD
n
n-1
SO
Dn+1
Dn
Dn
Dn-1
HOLDB
Figure 2-(c). HOLD timing
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Block Diagram
Datasheet
CSB
1
INSTRUCTION DECODE
CONTROL CLOCK
GENERATION
WRITE
VOLTAGE
DETECTION
8 Vcc
HIGH VOLTAGE
GENERATOR
SO
2
INSTRUCTION
REGISTER
INHIBITION
7 HOLDB
STATUS REGISTER
WPB
3
ADDRESS
REGISTER
DATA
16bit
ADDRESS
DECODER
READ/WRITE
AMP
16bit
6 SCK
512K
EEPROM
GND
4
REGISTER
8bit
8bit
5 SI
Figure 3. Block Diagram
Pin Configuration
(TOP VIEW)
Vcc
HOLDB SCK
SI
CSB
SO
WPB
GND
Figure 4. Pin Configuration
Pin Descriptions
Terminal
name
Vcc
GND
CSB
SCK
SI
SO
HOLDB
Input
/Output
-
-
Input
Input
Input
Output
Input
Function
Power source to be connected
All input / output reference voltage, 0V
Chip select input
Serial clock input
Ope code, address, and serial data input
Serial data output
Hold input
Command communications may be suspended
temporarily (HOLD status)
Write protect input
Write status register command is prohibited
WPB
Input
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