CY7C1318BV18, CY7C1320BV18
18-Mbit DDR-II SRAM 2-Word
Burst Architecture
Features
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Functional Description
The CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and
CY7C1320BV18 are 1.8V Synchronous Pipelined SRAMs
equipped with DDR-II architecture. The DDR-II consists of an
SRAM core with advanced synchronous peripheral circuitry and
a one-bit burst counter. Addresses for read and write are latched
on alternate rising edges of the input (K) clock. Write data is
registered on the rising edges of both K and K. Read data is
driven on the rising edges of C and C if provided, or on the rising
edge of K and K if C/C are not provided. Each address location
is associated with two 8-bit words in the case of CY7C1316BV18
and two 9-bit words in the case of CY7C1916BV18 that burst
sequentially into or out of the device. The burst counter always
starts with a ‘0’ internally in the case of CY7C1316BV18 and
CY7C1916BV18. For CY7C1318BV18 and CY7C1320BV18,
the burst counter takes in the least significant bit of the external
address and bursts two 18-bit words (in the case of
CY7C1318BV18) of two 36-bit words (in the case of
CY7C1320BV18) sequentially into or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs, D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need to capture data
separately from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
18-Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)
300 MHz clock for high bandwidth
2-word burst for reducing address bus frequency
Double Data Rate (DDR) interfaces
(data transferred at 600 MHz) at 300 MHz
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
Synchronous internally self-timed writes
1.8V core power supply with HSTL inputs and outputs
Variable drive HSTL output buffers
Expanded HSTL output voltage (1.4V–V
DD
)
Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)
Offered in both Pb-free and non Pb-free packages
JTAG 1149.1 compatible test access port
Delay Lock Loop (DLL) for accurate data placement
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Configurations
CY7C1316BV18 – 2M x 8
CY7C1916BV18 – 2M x 9
CY7C1318BV18 – 1M x 18
CY7C1320BV18 – 512K x 36
Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
x8
x9
x18
x36
300 MHz
300
815
820
855
930
278 MHz
278
775
780
805
855
250 MHz
250
705
710
730
775
200 MHz
200
575
580
600
635
167 MHz
167
490
490
510
540
Unit
MHz
mA
mA
mA
mA
Cypress Semiconductor Corporation
Document Number: 38-05621 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised October 21, 2010
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CY7C1318BV18, CY7C1320BV18
Logic Block Diagram (CY7C1316BV18)
A
(19:0)
LD
K
K
DOFF
20
Write Add. Decode
Read Add. Decode
Address
Register
Write
Reg
1M x 8 Array
Write
Reg
8
1M x 8 Array
CLK
Gen.
Output
Logic
Control
R/W
C
C
Read Data Reg.
16
Control
Logic
V
REF
R/W
NWS
[1:0]
8
8
Reg.
Reg.
Reg. 8
8
8
CQ
CQ
DQ
[7:0]
Logic Block Diagram (CY7C1916BV18)
A
(19:0)
LD
K
K
DOFF
20
Write Add. Decode
Read Add. Decode
Address
Register
Write
Reg
1M x 9 Array
Write
Reg
9
1M x 9 Array
CLK
Gen.
Output
Logic
Control
R/W
C
C
Read Data Reg.
18
Control
Logic
V
REF
R/W
BWS
[0]
9
9
Reg.
Reg.
Reg. 9
9
9
CQ
CQ
DQ
[8:0]
Document Number: 38-05621 Rev. *F
Page 2 of 30
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CY7C1318BV18, CY7C1320BV18
Logic Block Diagram (CY7C1318BV18)
A0
Burst
Logic
A
(19:0)
20
LD
K
K
19
Write Add. Decode
Read Add. Decode
A
(19:1)
Address
Register
Write
Reg
512K x 18 Array
Write
Reg
512K x 18 Array
18
CLK
Gen.
Output
Logic
Control
R/W
C
C
DOFF
Read Data Reg.
36
Control
Logic
V
REF
R/W
BWS
[1:0]
18
18
Reg.
Reg.
Reg. 18
18
18
CQ
CQ
DQ
[17:0]
Logic Block Diagram (CY7C1320BV18)
A0
Burst
Logic
A
(18:0)
19
LD
K
K
18
Write Add. Decode
Read Add. Decode
A
(18:1)
Address
Register
Write
Reg
256K x 36 Array
Write
Reg
256K x 36 Array
36
CLK
Gen.
Output
Logic
Control
R/W
C
C
DOFF
Read Data Reg.
72
Control
Logic
V
REF
R/W
BWS
[3:0]
36
36
Reg.
Reg.
Reg. 36
36
36
CQ
CQ
DQ
[35:0]
Document Number: 38-05621 Rev. *F
Page 3 of 30
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CY7C1318BV18, CY7C1320BV18
Contents
Features ............................................................................. 1
Configurations .................................................................. 1
Functional Description ..................................................... 1
Selection Guide ................................................................ 1
Logic Block Diagram (CY7C1316BV18) .......................... 2
Logic Block Diagram (CY7C1916BV18) .......................... 2
Logic Block Diagram (CY7C1318BV18) .......................... 3
Logic Block Diagram (CY7C1320BV18) .......................... 3
Pin Configuration ............................................................. 4
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout .................. 4
Pin Definitions .................................................................. 6
Functional Overview ........................................................ 8
Read Operations ......................................................... 8
Write Operations ......................................................... 8
Byte Write Operations ................................................. 8
Single Clock Mode ...................................................... 8
DDR Operation ............................................................ 8
Depth Expansion ......................................................... 8
Programmable Impedance .......................................... 9
Echo Clocks ................................................................ 9
DLL .............................................................................. 9
Application Example ........................................................ 9
Truth Table ...................................................................... 10
Burst Address Table
(CY7C1318BV18, CY7C1320BV18) ................................ 10
Write Cycle Descriptions ............................................... 10
Write Cycle Descriptions ............................................... 11
Write Cycle Descriptions ............................................... 11
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 12
Disabling the JTAG Feature ...................................... 12
Test Access Port—Test Clock ................................... 12
Test Mode Select (TMS) ........................................... 12
Test Data-In (TDI) ..................................................... 12
Test Data-Out (TDO) ................................................. 12
Performing a TAP Reset ........................................... 12
TAP Registers ........................................................... 12
TAP Instruction Set ................................................... 12
TAP Controller State Diagram ....................................... 14
TAP Controller Block Diagram ...................................... 15
TAP Electrical Characteristics ...................................... 15
TAP AC Switching Characteristics ............................... 16
TAP Timing and Test Conditions .................................. 16
Identification Register Definitions ................................ 17
Scan Register Sizes ....................................................... 17
Instruction Codes ........................................................... 17
Boundary Scan Order .................................................... 18
Power Up Sequence in DDR-II SRAM ........................... 19
Power Up Sequence ................................................. 19
DLL Constraints ......................................................... 19
Maximum Ratings ........................................................... 20
Operating Range ............................................................. 20
Electrical Characteristics ............................................... 20
DC Electrical Characteristics ..................................... 20
AC Electrical Characteristics ..................................... 21
Capacitance .................................................................... 22
Thermal Resistance ........................................................ 22
Switching Characteristics .............................................. 23
Switching Waveforms .................................................... 25
Ordering Information ...................................................... 26
Package Diagram ............................................................ 27
Document History Page ................................................. 28
Sales, Solutions, and Legal Information ...................... 29
Worldwide Sales and Design Support ....................... 29
Products .................................................................... 29
PSoC Solutions ......................................................... 29
Document Number: 38-05621 Rev. *F
Page 4 of 30
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CY7C1318BV18, CY7C1320BV18
Pin Configuration
The pin configuration for CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and CY7C1320BV18 follow.
[1]
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C1316BV18 (2M x 8)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/72M
NC
NC
NC
NC
NC
NC
V
REF
NC
NC
DQ6
NC
NC
NC
TCK
3
A
NC
NC
NC
DQ4
NC
DQ5
V
DDQ
NC
NC
NC
NC
NC
DQ7
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
NWS
1
NC/288M
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC/144M
NWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
NC/36M
NC
NC
NC
NC
NC
NC
V
REF
DQ1
NC
NC
NC
NC
NC
TMS
11
CQ
DQ3
NC
NC
DQ2
NC
NC
ZQ
NC
NC
DQ0
NC
NC
NC
TDI
CY7C1916BV18 (2M x 9)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
DOFF
NC
NC
NC
NC
NC
NC
TDO
2
NC/72M
NC
NC
NC
NC
NC
NC
V
REF
NC
NC
DQ6
NC
NC
NC
TCK
3
A
NC
NC
NC
DQ4
NC
DQ5
V
DDQ
NC
NC
NC
NC
NC
DQ7
A
4
R/W
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
5
NC
NC/288M
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
6
K
K
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
A
C
C
7
NC/144M
BWS
0
A
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
A
A
A
8
LD
A
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
A
A
9
A
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
A
10
NC/36M
NC
NC
NC
NC
NC
NC
V
REF
DQ1
NC
NC
NC
NC
NC
TMS
11
CQ
DQ3
NC
NC
DQ2
NC
NC
ZQ
NC
NC
DQ0
NC
NC
DQ8
TDI
Note
1. NC/36M, NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 38-05621 Rev. *F
Page 5 of 30
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