CY7C1372BV25
CY7C1370BV25
512K x 36/1M x 18 Pipelined SRAM
with NoBL™ Architecture
Features
• Zero Bus Latency, no dead cycles between Write and
Read cycles
• Fast clock speed: 200,167, 150, and 133 MHz
• Fast access time: 3.0, 3.4, 3.8, 4.2 ns
• Internally synchronized registered outputs eliminate
the need to control OE
• Single 2.5V +5%
• Single WE (Read/Write) control pin
• Positive clock-edge triggered, address, data, and
control signal registers for fully pipelined applications
• Interleaved or linear 4-word burst capability
• Individual byte Write (BWS
a
–BWS
d
) control (may be
tied LOW)
• CEN pin to enable clock and suspend operations
• Three chip enables for simple depth expansion
• JTAG boundary scan for BGA packaging version
• Available in 119-ball bump BGA and 100-pin TQFP
packages
• Automatic power-down available using zz mode or CE
deselect
inputs include all addresses, all data inputs, depth-expansion
Chip Enables (CE
1
, CE
2
and CE
3
), cycle start input (ADV/LD),
Clock Enable (CEN), Byte Write Selects (BWS
a
, BWS
b
, BWS
c
and BWS
d
), and Read-Write control (WE). BWS
c
and BWS
d
apply to CY7C1370BV25 only.
Address and control signals are applied to the SRAM during
one clock cycle, and two cycles later, its associated data
occurs, either Read or Write.
A Clock Enable (CEN) pin allows operation of the
CY7C1370BV25/CY7C1372BV25 to be suspended as long as
necessary. All synchronous inputs are ignored when (CEN) is
HIGH and the internal device registers will hold their previous
values.
There are three Chip Enable (CE
1
, CE
2
, CE
3
) pins that allow
the user to deselect the device when desired. If any one of
these three are not active when ADV/LD is LOW, no new
memory operation can be initiated and any burst cycle in
progress is stopped. However, any pending data transfers
(Read or Write) will be completed. The data bus will be in
high-impedance state two cycles after chip is deselected or a
Write cycle is initiated.
The CY7C1370BV25 and CY7C1372BV25 have an on-chip
two-bit burst counter. In the burst mode, the CY7C1370BV25
and CY7C1372BV25 provide four cycles of data for a single
address presented to the SRAM. The order of the burst
sequence is defined by the MODE input pin. The MODE pin
selects between linear and interleaved burst sequence. The
ADV/LD signal is used to load a new external address
(ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH)
Output Enable (OE) and burst sequence select (MODE) are
the asynchronous signals. OE can be used to disable the
outputs at any given time. ZZ may be tied to LOW if it is not
used.
Four pins are used to implement JTAG test capabilities. The
JTAG circuitry is used to serially shift data to and from the
device. JTAG inputs use LVTTL/LVCMOS levels to shift data
during this testing mode of operation.
Functional Description
The CY7C1370BV25 and CY7C1372BV25 SRAMs are
designed to eliminate dead cycles when transitions from
READ to WRITE or vice versa. These SRAMs are optimized
for 100 percent bus utilization and achieves Zero Bus Latency.
They integrate 524,288 × 36 and 1,048,576 × 18 SRAM cells,
respectively, with advanced synchronous peripheral circuitry
and a 2-bit counter for internal burst operation. The Cypress
Synchronous Burst SRAM family employs high-speed,
low-power CMOS designs using advanced single layer
polysilicon, threelayer metal technology. Each memory cell
consists of six transistors.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
Logic Block Diagram
CLK
CE
ADV/LD
A
x
CEN
CE
1
CE
2
CE
3
WE
BWS
x
Mode
X = a, b, c, d
X = a, b, c, d
X = a, b, c, d
X = a, b
X = a, b
X = a, b
D
Data-In REG.
Q
OUTOUT
REGISTERS
and LOGIC
CY7C1370
A
X
DQ
X
DP
X
BWS
X
X = 18:0
CY7C1372
X = 19:0
CONTROL
and WRITE
LOGIC
256K × 36/
512K × 18
MEMORY
ARRAY
DQ
x
DP
x
OE
Cypress Semiconductor Corporation
Document #: 38-05252 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134
• 408-943-2600
Revised April 8, 2002
CY7C1372BV25
CY7C1370BV25
Selection Guide
200 MHz
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
3.0
280
30
167 MHz
3.4
230
30
150 MHz
3.8
190
30
133 MHz
4.2
160
30
Unit
ns
mA
mA
Pin Configurations
100-pin TQFP Packages
A
A
CE
1
CE
2
BWSd
BWSc
BWSb
BWSa
CE
3
V
DD
V
SS
CLK
WE
CEN
OE
ADV/LD
A
A
A
A
CE
1
CE
2
NC
NC
BWSb
BWSa
CE
3
V
DD
V
SS
CLK
WE
CEN
OE
ADV/LD
A
A
DPb
DQb
DQb
V
DDQ
V
SS
A
A
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
DPc
DQc
DQc
V
DDQ
V
SS
DQc
DQc
DQc
DQc
V
SS
V
DDQ
DQc
DQc
NC
V
DD
NC
V
SS
DQd
DQd
V
DDQ
V
SS
DQd
DQd
DQd
DQd
V
SS
V
DDQ
DQd
DQd
DPd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1370BV25
(512K × 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQb
DQb
V
SS
V
DDQ
DQb
DQb
NC
V
DD
NC
V
SS
DQb
DQb
V
DDQ
V
SS
DQb
DQb
DPb
NC
V
SS
V
DDQ
NC
NC
NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
DQb
DQb
DQb
DQb
V
SS
V
DDQ
DQb
DQb
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DDQ
V
SS
DQa
DQa
DQa
DQa
V
SS
V
DDQ
DQa
DQa
DPa
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
V
DDQ
V
SS
NC
DPa
DQa
DQa
V
SS
V
DDQ
DQa
DQa
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DDQ
V
SS
DQa
DQa
NC
NC
V
SS
V
DDQ
NC
NC
NC
CY7C1372BV25
(1M × 18)
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
MODE
A
A
A
A
A
1
A
0
DNU
DNU
V
SS
V
DD
DNU
DNU
A
A
A
A
A
A
A
Document #: 38-05252 Rev. **
MODE
A
A
A
A
A
1
A
0
DNU
DNU
V
S
V
DD
DNU
DNU
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Page 2 of 26
CY7C1372BV25
CY7C1370BV25
Pin Configurations
(continued)
119-ball Bump BGA
CY7C1370BV25
(512K × 36)–7 × 17 BGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
c
DQ
c
V
DDQ
DQ
c
DQ
c
V
DDQ
DQ
d
DQ
d
V
DDQ
DQ
d
DQ
d
NC
NC
V
DDQ
2
A
CE
2
A
DP
c
DQ
c
DQ
c
DQ
c
DQ
c
V
DD
DQ
d
3
A
A
A
V
SS
V
SS
V
SS
BWS
c
V
SS
NC
V
SS
BWS
d
V
SS
V
SS
V
SS
MODE
A
TDI
4
A
ADV/LD
V
DD
NC
CE
1
OE
A
WE
V
DD
CLK
NC
CEN
A1
A0
V
DD
A
TCK
5
A
A
A
V
SS
V
SS
V
SS
BWS
b
V
SS
NC
V
SS
BWS
a
V
SS
V
SS
V
SS
NC
A
TDO
6
A
CE
3
A
DP
b
DQ
b
DQ
b
DQ
b
DQ
b
V
DD
DQ
a
DQ
a
DQ
a
DQ
a
DP
a
A
32M
NC
7
V
DDQ
NC
NC
DQ
b
DQ
b
V
DDQ
DQ
b
DQ
b
V
DDQ
DQ
a
DQ
a
V
DDQ
DQ
a
DQ
a
NC
ZZ
V
DDQ
DQ
d
DQ
d
DQ
d
DP
d
A
64M
TMS
CY7C1372BV25
(1M × 18)–7 × 17 BGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
b
NC
V
DDQ
NC
DQ
b
V
DDQ
NC
DQ
b
V
DDQ
DQ
b
NC
NC
64M
V
DDQ
2
A
CE
2
A
NC
DQ
b
NC
DQ
b
NC
V
DD
DQ
b
NC
DQ
b
NC
DP
b
A
A
TMS
3
A
A
A
V
SS
V
SS
V
SS
BWS
b
V
SS
NC
V
SS
V
SS
V
SS
V
SS
V
SS
MODE
A
TDI
4
A
ADV/LD
V
DD
NC
CE
1
OE
A
WE
V
DD
CLK
NC
CEN
A1
A0
V
DD
32M
TCK
5
A
A
A
V
SS
V
SS
V
SS
V
SS
V
SS
NC
V
SS
BWS
a
V
SS
V
SS
V
SS
NC
A
TDO
6
A
CE
3
A
DP
a
NC
DQ
a
NC
DQ
a
V
DD
NC
DQ
a
NC
DQ
a
NC
A
A
NC
7
V
DDQ
NC
NC
NC
DQ
a
V
DDQ
DQ
a
NC
V
DDQ
DQ
a
NC
V
DDQ
NC
DQ
a
NC
ZZ
V
DDQ
Document #: 38-05252 Rev. **
Page 3 of 26
CY7C1372BV25
CY7C1370BV25
Pin Configurations
(continued)
165-ball Bump FBGA
CY7C1370BV25
(512K × 36)–11 × 15 FBGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
DPc
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
DPd
NC
MODE
2
A
A
NC
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
NC
64M
32M
3
CE
1
CE
2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
4
BWSc
BWSd
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
5
BWSb
BWSa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
DNU
DNU
6
CE
3
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
A0
7
CEN
WE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
DNU
DNU
8
ADV/LD
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
9
A
A
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
10
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
11
NC
128M
DPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
DPa
NC
A
CY7C1372BV25
(1M × 18)–11 × 15 FBGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC
NC
NC
NC
NC
NC
NC
NC
DQb
DQb
DQb
DQb
DPb
NC
MODE
2
A
A
NC
DQb
DQb
DQb
DQb
V
DD
NC
NC
NC
NC
NC
64M
32M
3
CE
1
CE
2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
4
BWSb
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
5
NC
BWSa
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
DNU
DNU
6
CE
3
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
A1
A0
7
CEN
WE
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
DNU
DNU
8
ADV/LD
OE
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
A
9
A
A
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
10
A
A
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
A
A
11
A
128M
DPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
NC
NC
NC
A
Document #: 38-05252 Rev. **
Page 4 of 26
CY7C1372BV25
CY7C1370BV25
Pin Definitions
Pin Name
A0
A1
A
BWS
a
BWS
b
BWS
c
BWS
d
WE
ADV/LD
I/O Type
Input-
Synchronous
Input-
Synchronous
Pin Description
Address Inputs used to select one of the 524,288/1048576 address locations. Sampled at
the rising edge of CLK.
Byte Write Select Inputs, active LOW.
Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BWS
a
controls DQ
a
and DP
a
, BWS
b
controls DQ
b
and
DP
b
, BWS
c
controls DQ
c
and DP
c
, BWS
d
controls DQ
d
and DP
d
.
Write Enable Input, active LOW.
Sampled on the rising edge of CLK if CEN is active LOW.
This signal must be asserted LOW to initiate a Write sequence.
Advance/Load Input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW,
a new address can be loaded into the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.
Clock Input.
Used to capture all synchronous inputs to the device. CLK is qualified with
CEN. CLK is only recognized if CEN is active LOW.
Chip Enable 1 Input, active LOW.
Sampled on the rising edge of CLK. Used in conjunction
with CE
2
and CE
3
to select/deselect the device.
Chip Enable 2 Input, active HIGH.
Sampled on the rising edge of CLK. Used in conjunction
with CE
1
and CE
3
to select/deselect the device.
Chip Enable 3 Input, active LOW.
Sampled on the rising edge of CLK. Used in conjunction
with CE
1
and CE
2
to select/deselect the device.
Output Enable, active LOW.
Combined with the synchronous logic block inside the device
to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as
outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE
is masked during the data portion of a Write sequence, during the first clock when emerging
from a deselected state and when the device has been deselected.
Clock Enable Input, active LOW.
When asserted LOW the clock signal is recognized by
the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does
not deselect the device, CEN can be used to extend the previous cycle when required.
Bidirectional Data I/O Lines.
As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory
location specified by A
X
during the previous clock rise of the Read cycle. The direction of
the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the
pins can behave as outputs. When HIGH, DQ
a
–DQ
d
are placed in a three-state condition.
The outputs are automatically three-stated during the data portion of a Write sequence,
during the first clock when emerging from a deselected state, and when the device is
deselected, regardless of the state of OE. DQ a,b,c and d are eight bits wide
Bidirectional Data Parity I/O Lines.
Functionally, these signals are identical to DQ
[31:0]
.
During Write sequences, DP
a
is controlled by BWS
a
, DP
b
is controlled by BWS
b
, DP
c
is
controlled by BWS
c
, and DP
d
is controlled by BWS
d
.DP a,b,c and d are 1 bit wide
ZZ “sleep” Input.
This active HIGH input places the device in a non-time critical “sleep”
condition with data integrity preserved.
Mode Input.
Selects the burst order of the device. Tied HIGH selects the interleaved burst
order. Pulled LOW selects the linear burst order. MODE should not change states during
operation. When left floating MODE will default HIGH, to an interleaved burst order.
Power supply inputs to the core of the device.
Power supply for the I/O circuitry.
Ground for the device.
Should be connected to ground of the system.
Serial data-out to the JTAG circuit.
Delivers data on the negative edge of TCK (BGA only).
Serial data-In to the JTAG circuit.
Sampled on the rising edge of TCK (BGA Only).
Input-
Synchronous
Input-
Synchronous
CLK
CE
1
CE
2
CE
3
OE
Input-Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
CEN
Input-
Synchronous
I/O-
Synchronous
DQ
a
DQ
b
DQ
c
DQ
d
DP
a
DP
b
DP
c
DP
d
ZZ
MODE
I/O-
Synchronous
Input-
Asynchronous
Input Pin
V
DD
V
DDQ
V
SS
TDO
TDI
Power Supply
I/O Power Supply
Ground
JTAG serial output
Synchronous
JTAG serial input
Synchronous
Document #: 38-05252 Rev. **
Page 5 of 26
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