NCP5211A
Low Voltage Synchronous
Buck Controller
The NCP5211A is a low voltage synchronous buck controller. It
contains all required circuitry for a synchronous buck converter using
external N−Channel MOSFETs. High current internal gate drivers are
capable of driving low R
DS(on)
NFETs for better efficiency. The
NCP5211A is in a 14 pin package to minimize PCB area.
The NCP5211A provides overcurrent protection, undervoltage
lockout, soft start and built in adaptive nonoverlap. The NCP5211A is
adjustable over a frequency range of 150 kHz to 750 kHz. This gives
the designer more flexibility to make efficiency and component size
compromises. The NCP5211A will operate on a single supply or a
separate boost supply.
Features
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MARKING
DIAGRAM
14
SOIC−14
D SUFFIX
CASE 751A
1
B
WL
Y
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
NCP5211A
BWLYWW
•
Switching Regulator Controller
−
N−Channel Synchronous Buck Design
−
1.0 Amp Gate Drive Capability
−
200 ns Transient Response
−
Programmable Operating Frequency of 150 kHz−750 kHz
−
0.8 V 1% Internal Reference
−
Lossless Inductor Sensing Overcurrent Protection
−
Cycle−by−Cycle Short Circuit Protection
−
Programmable Soft Start
−
40 ns GATE Rise and Fall Times (3.3 nF Load)
−
70 ns Adaptive FET Nonoverlap Time
−
Differential Remote Sense Capability
•
System Power Management
−
Operation with a Conversion Rail of 5.0 V or 12 V
−
Undervoltage Lockout
−
On/Off Control Through Use of the COMP Pin
−
Max Duty Cycle Clamped to 70% for Forward Converter Control
Applications
PIN CONNECTIONS
1
GATE(H)
BST
LGND
V
FFB
V
FB
COMP
SGND
PGND
GATE(L)
V
C
IS+
IS−
V
CC
R
OSC
ORDERING INFORMATION
Device
NCP5211AD
NCP5211ADR2
Package
SO−14
SO−14
Shipping†
55 Units/Rail
2500 Tape & Reel
•
•
•
•
Set Top Devices
Forward Converters
Buck Converters
Point of Load Regulation
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2003
1
December, 2003 − Rev. 3
Publication Order Number:
NCP5211A/D
NCP5211A
5.0 V
+
100
µF/10
V
×
3
NTMS7N03
0.1
µF
V
C
V
CC
COMP
0.1
µF
51 k
0.1
µF
R
OSC
NCP5211A
IS+
IS−
SGND
LGND
10
V
FFB
V
FB
2.15 k
1.0 k
1.0%
680 pF
SENSE−
NOTE:
Resistance in Ohms
1.0%
SENSE+
BST
GATE(H)
GATE(L)
PGND
NTMS7N03
0.1
µF
4.7 k
+
2.9
µH
2.5 V/8 A
+V
OUT
100
µF/10
V
×
2
10
−V
OUT
Return
Figure 1. Application Diagram, 5.0 V to 2.5 V/8 A Converter with Differential Remote Sense
MAXIMUM RATINGS*
Rating
Operating Junction Temperature, T
J
Lead Temperature Soldering:
Storage Temperature Range, T
S
Package Thermal Resistance:
Junction−to−Case, R
θJC
Junction−to−Ambient, R
θJA
ESD Capability − All pins except R
OSC
(Human Body Model)
(Machine Model)
ESD Capability − R
OSC
Pin Only (Human Body Model)
(Machine Model)
JEDEC Moisture Sensitivity
1. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed by not exceeding 150°C T
J
.
Reflow: (SMD styles only) (Note 1)
Value
150
230 peak
−65 to +150
30
125
2.0
200
500
150
Level 1
Unit
°C
°C
°C
°C/W
°C/W
kV
V
V
V
−
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2
NCP5211A
MAXIMUM RATINGS
(Voltage with respect to Logic Ground)
Pin Name
IC Power Input
Power input for the low side driver
Power Supply input for the high
side driver
Compensation Capacitor
Voltage Feedback Input
Oscillator Resistor
Fast Feedback Input
High−Side FET Driver
Pin Symbol
V
CC
V
C
BST
V
MAX
16 V
16 V
20 V
V
MIN
−0.3 V
−0.3 V
−0.3 V
I
SOURCE
N/A
N/A
N/A
I
SINK
50 mA DC
1.5 A Peak, 200 mA DC
1.5 A Peak, 200 mA DC
COMP
V
FB
R
OSC
V
FFB
GATE(H)
6.0 V
6.0 V
6.0 V
6.0 V
20 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−0.3 V
−2.0 V for 50 ns
−0.3 V
−2.0 V for 50 ns
−0.3 V
−0.3 V
−0.2 V
N/A
−0.2 V
1.0 mA
1.0 mA
1.0 mA
1.0 mA
1.5 A Peak
200 mA DC
1.5 A Peak
200 mA DC
1.0 mA
1.0 mA
1.5 A Peak, 200 mA DC
100 mA
1.0 mA
1.0 mA
1.0 mA
1.0 mA
1.0 mA
1.5 A Peak
200 mA DC
1.5 A Peak
200 mA DC
1.0 mA
1.0 mA
N/A
N/A
1.0 mA
Low−Side FET Driver
GATE(L)
16 V
Positive Current Sense
Negative Current Sense
Power Ground
Logic Ground
Sense Ground
IS+
IS−
PGND
LGND
SGND
6.0 V
6.0 V
0.2 V
N/A
0.2 V
ELECTRICAL CHARACTERISTICS
(−40°C < T
A
< 85°C; −40°C < T
J
< 125°C; 4.5 V < V
CC
, V
C
< 14 V;
7.0 V < BST < 20 V; C
GATE(H)
= C
GATE(L)
= 3.3 nF; R
OSC
= 51 k; C
COMP
= 0.1
µF,
unless otherwise specified.)
Characteristic
Error Amplifier
V
FB
Bias Current
COMP Source Current
COMP SINK Current
Open Loop Gain
Unity Gain Bandwidth
PSRR @ 1.0 kHz
Output Transconductance
Output Impedance
Reference Voltage
V
FB
= 0 V
V
FB
= 0.6 V
V
FB
= 1.2 V
(Note 2)
C = 0.1
µF,
(Note 2)
(Note 2)
(Note 2)
(Note 2)
−0.1 V < SGND < 0.1 V,
COMP = V
FB
, Measure
V
FB
to SGND
V
FB
= 0.6 V
V
FB
= 1.2 V
−
−
−40
≤
T
J
≤
125°C
25
≤
T
J
≤
110°C
−
15
15
−
−
−
−
−
0.788
0.792
2.5
−
500
0.2
0.1
30
30
98
50
70
32
2.5
0.8
0.8
3.0
0.1
750
0.4
1.0
60
60
−
−
−
−
−
0.812
0.808
−
0.2
1000
0.6
V
V
µA
V
µA
µA
µA
dB
kHz
dB
mmho
MΩ
V
Test Conditions
Min
Typ
Max
Unit
COMP Max Voltage
COMP Min Voltage
COMP Discharge Current in UVLO
COMP Threshold to Start Gate Drive
2. Guaranteed by design. Not tested in production.
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3
NCP5211A
ELECTRICAL CHARACTERISTICS
(continued)
(−40°C < T
A
< 85°C; −40°C < T
J
< 125°C; 4.5 V < V
CC
, V
C
< 14 V;
7.0 V < BST < 20 V; C
GATE(H)
= C
GATE(L)
= 3.3 nF; R
OSC
= 51 k; C
COMP
= 0.1
µF,
unless otherwise specified.)
Characteristic
GATE(H) and GATE(L)
High Voltage (AC)
GATE(L),
GATE(H)
0.5 nF < C
GATE(H)
= C
GATE(L)
< 10 nF
GATE(L) or GATE(H)
0.5 nF < C
GATE(H)
; C
GATE(L)
< 10 nF
V
C
= BST = 10 V, Measure:
1.0 V < GATE(L) < 9.0 V,
1.0 V < GATE(H) < 9.0 V
V
C
= BST = 10 V, Measure:
1.0 V < GATE(L) < 9.0 V,
1.0 V < GATE(H) < 9.0 V
GATE(H) < 2.0 V, GATE(L) > 2.0 V
GATE(L) < 2.0 V, GATE(H) > 2.0 V
Resistance to PGND
V
C
− 0.5
BST − 0.5
−
−
−
−
V
Test Conditions
Min
Typ
Max
Unit
Low Voltage (AC)
Rise Time
−
40
0.5
80
V
ns
Fall Time
−
40
80
ns
GATE(H) to GATE(L) Delay
GATE(L) to GATE(H) Delay
GATE(H)/(L) Pull−Down
Overcurrent Protection
Current Limit Threshold
IS+ Bias Current
IS− Bias Current
PWM Comparator
Transient Response
PWM Comparator Offset
Artificial Ramp
V
FFB
Bias Current
V
FFB
Max Input
Minimum Pulse Width
Oscillator
Switching Frequency
R
OSC
Voltage
Max Duty Cycle
General Electrical Specifications
V
CC
Supply Current
BST Supply Current
V
C
Supply Current
Start Threshold
Stop Threshold
Hysteresis
Sense Ground Current
40
40
20
70
70
50
110
110
115
ns
ns
kΩ
0 V < IS+ < 4.5 V, 0 V < IS− < 4.5 V
0 V < IS+ < 4.5 V
0 V < IS− < 4.5 V
54
−1.0
−1.0
60
0.1
0.1
66
1.0
1.0
mV
µA
µA
COMP = 0 − 1.5 V, V
FFB
, 20 mV overdrive
V
FB
= V
FFB
= 0 V; Increase COMP until
GATE(H) starts switching
Duty Cycle = 70% (Note 3)
V
FFB
= 0 V
(Note 3)
−
−
0.425
30
−
1.1
−
100
0.475
55
0.1
−
−
200
0.525
80
1.0
−
200
ns
V
mV
µA
V
ns
R
OSC
= 51 k
−
V
COMP
> V
FFB
+ 1.0 V
270
1.21
65
300
1.25
70
330
1.29
75
kHz
V
%
COMP = 0 V (no switching)
COMP = 0 V (no switching)
COMP = 0 V (no switching)
GATE(H) Switching, COMP Charging
GATE(H) Not Switching, COMP Not Charging
Start−Stop
−
−
−
−
4.03
3.89
100
−
7.0
2.0
2.0
4.18
4.04
140
0.15
8.3
3.0
3.0
4.33
4.19
180
1.00
mA
mA
mA
V
V
mV
mA
3. Guaranteed by design. Not tested in production.
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4
NCP5211A
PACKAGE PIN DESCRIPTION
PIN NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIN SYMBOL
GATE(H)
BST
LGND
V
FFB
V
FB
COMP
SGND
R
OSC
V
CC
IS−
IS+
V
C
GATE(L)
PGND
FUNCTION
High Side Switch FET driver pin. Capable of delivering peak currents of 1.0 A.
Power supply input for the high side driver.
Reference ground. All control circuits are referenced to this pin. IC substrate connection.
Input for the PWM comparator.
Error amplifier input.
Error Amp output. PWM Comparator reference input. A capacitor to LGND provides error amp
compensation.
Internal reference is connected to this ground. Connect directly at the load for ground remote
sensing.
A resistor from this pin to SGND sets switching frequency.
Input Power Supply Pin. It supplies power to control circuitry. A 0.1
µF
decoupling cap is
recommended.
Negative input for overcurrent comparator.
Positive input for overcurrent comparator.
Power supply input for the low side driver.
Low Side Synchronous FET driver pin. Capable of delivering peak currents of 1.0 A.
High Current ground for the GATE(H) and GATE(L) pins.
0.5 V
−
−
PWM Comparator
Ramp
+
V
FFB
Σ
+
PWM FF
Reset Dominant
R
STOP
Q
BST
GATE(H)
COMP
V
FB
Error Amp
−
+
−
+
0.8 V
UVLO
Comparator
+
SGND
OC FF
Reset Dominant
R
Q
PGND
R
OSC
V
START
V
CC
OC
Comparator
60 mV
IS−
LGND
+
+
IS+
0.4 V
Figure 2. NCP5211A Block Diagram
−
START
OSC
S
START
Q
V
C
GATE(L)
R
OSC
−
−
S
+
−
Q
COMP Comp
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5
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