CY7C1422AV18, CY7C1429AV18
CY7C1423AV18, CY7C1424AV18
36-Mbit DDR-II SIO SRAM 2-Word
Burst Architecture
36-Mbit DDR-II SIO SRAM 2-Word Burst Architecture
Features
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Functional Description
The CY7C1422AV18, CY7C1429AV18, CY7C1423AV18, and
CY7C1424AV18 are 1.8 V Synchronous Pipelined SRAMs,
equipped with Double Data Rate Separate IO (DDR-II SIO)
architecture. The DDR-II SIO consists of two separate ports: the
read port and the write port to access the memory array. The
read port has data outputs to support read operations and the
write port has data inputs to support write operations. The DDR-II
SIO has separate data inputs and data outputs to completely
eliminate the need to “turn-around” the data bus required with
common IO devices. Access to each port is accomplished
through a common address bus. Addresses for read and write
are latched on alternate rising edges of the input (K) clock. Write
data is registered on the rising edges of both K and K. Read data
is driven on the rising edges of C and C if provided, or on the
rising edge of K and K if C/C are not provided. Each address
location is associated with two 8-bit words in the case of
CY7C1422AV18, two 9-bit words in the case of CY7C1429AV18,
two 18-bit words in the case of CY7C1423AV18, and two 36-bit
words in the case of CY7C1424AV18 that burst sequentially into
or out of the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs are tightly matched to the
two output echo clocks CQ/CQ, eliminating the need to capture
data separately from each individual DDR-II SIO SRAM in the
system design. Output data clocks (C/C) enable maximum
system clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
36-Mbit density (4M × 8, 4M × 9, 2M × 18, 1M × 36)
300 MHz clock for high bandwidth
2-word burst for reducing address bus frequency
Double Data Rate (DDR) interfaces
(data transferred at 600 MHz) at 300 MHz
Two input clocks (K and K) for precise DDR timing
❐
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock
skew and flight time mismatches
Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
Synchronous internally self-timed writes
1.8V core power supply with HSTL inputs and outputs
Variable drive HSTL output buffers
Expanded HSTL output voltage (1.4V–V
DD
)
Available in 165-Ball FBGA package (15 x 17 x 1.4 mm)
Offered in both Pb-free and non Pb-free packages
JTAG 1149.1 compatible test access port
Delay Lock Loop (DLL) for accurate data placement
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Configurations
CY7C1422AV18 – 4M × 8
CY7C1429AV18 – 4M × 9
CY7C1423AV18 – 2M × 18
CY7C1424AV18 – 1M × 36
Cypress Semiconductor Corporation
Document Number: 38-05617 Rev. *I
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised December 3, 2010
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CY7C1422AV18, CY7C1429AV18
CY7C1423AV18, CY7C1424AV18
Logic Block Diagram (CY7C1422AV18)
D
[7:0]
8
Write Add. Decode
Read Add. Decode
A
(20:0)
21
Address
Register
Write
Data Reg
Write
Data Reg
2M x 8 Array
2M x 8 Array
LD
Control
Logic
R/W
C
C
CQ
K
K
DOFF
R/W
V
REF
LD
NWS
[1:0]
Control
Logic
CLK
Gen.
Read Data Reg.
16
8
8
Reg.
Reg.
Reg. 8
8
8
CQ
Q
[7:0]
Logic Block Diagram (CY7C1429AV18)
D
[8:0]
9
Write Add. Decode
Read Add. Decode
A
(20:0)
21
Address
Register
Write
Data Reg
Write
Data Reg
2M x 9 Array
2M x 9 Array
LD
Control
Logic
R/W
C
C
CQ
K
K
DOFF
R/W
V
REF
LD
BWS
[0]
Control
Logic
CLK
Gen.
Read Data Reg.
18
9
9
Reg.
Reg.
Reg. 9
9
9
CQ
Q
[8:0]
Document Number: 38-05617 Rev. *I
Page 2 of 33
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CY7C1422AV18, CY7C1429AV18
CY7C1423AV18, CY7C1424AV18
Logic Block Diagram (CY7C1423AV18)
D
[17:0]
18
Write Add. Decode
Read Add. Decode
A
(19:0)
20
Address
Register
Write
Data Reg
Write
Data Reg
1M x 18 Array
1M x 18 Array
LD
Control
Logic
R/W
C
C
CQ
K
K
DOFF
R/W
V
REF
LD
BWS
[1:0]
Control
Logic
CLK
Gen.
Read Data Reg.
36
18
18
Reg.
Reg.
Reg. 18
18
CQ
18
Q
[17:0]
Logic Block Diagram (CY7C1424AV18)
D
[35:0]
36
Write Add. Decode
Read Add. Decode
A
(18:0)
19
Address
Register
Write
Data Reg
Write
Data Reg
512K x 36 Array
512K x 36 Array
LD
Control
Logic
R/W
C
C
CQ
K
K
DOFF
R/W
V
REF
LD
BWS
[3:0]
Control
Logic
CLK
Gen.
Read Data Reg.
72
36
36
Reg.
Reg.
Reg. 36
36
CQ
36
Q
[35:0]
Document Number: 38-05617 Rev. *I
Page 3 of 33
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CY7C1422AV18, CY7C1429AV18
CY7C1423AV18, CY7C1424AV18
Contents
Selection Guide ................................................................ 5
Pin Configuration ............................................................. 6
165-ball FPBGA (15 × 17 × 1.4 mm) Pinout ................ 6
Pin Definitions .................................................................. 8
Functional Overview ...................................................... 10
Read Operations ....................................................... 10
Write Operations ....................................................... 10
Byte Write Operations ............................................... 10
Single Clock Mode .................................................... 10
DDR Operation .......................................................... 10
Depth Expansion ....................................................... 10
Programmable Impedance ........................................ 10
Echo Clocks .............................................................. 10
DLL ............................................................................ 11
Application Example ...................................................... 11
Truth Table ...................................................................... 12
Write Cycle Descriptions ............................................... 12
Write Cycle Descriptions ............................................... 13
Write Cycle Descriptions ............................................... 13
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 14
Disabling the JTAG Feature ...................................... 14
Test Access Port—Test Clock ................................... 14
Test Mode Select (TMS) ........................................... 14
Test Data-In (TDI) ..................................................... 14
Test Data-Out (TDO) ................................................. 14
Performing a TAP Reset ........................................... 14
TAP Registers ........................................................... 14
TAP Instruction Set ................................................... 14
TAP Controller State Diagram ....................................... 16
TAP Controller Block Diagram ...................................... 17
TAP Electrical Characteristics ...................................... 17
TAP AC Switching Characteristics ............................... 18
TAP Timing and Test Conditions .................................. 18
Identification Register Definitions ................................ 19
Scan Register Sizes ....................................................... 19
Instruction Codes ........................................................... 19
Boundary Scan Order .................................................... 20
Power Up Sequence in DDR-II SRAM ........................... 21
Power Up Sequence ................................................. 21
DLL Constraints ......................................................... 21
Maximum Ratings ........................................................... 22
Operating Range ............................................................. 22
Electrical Characteristics ............................................... 22
DC Electrical Characteristics ..................................... 22
AC Electrical Characteristics ..................................... 23
Capacitance .................................................................... 24
Thermal Resistance ........................................................ 24
Switching Characteristics .............................................. 25
Switching Waveforms .................................................... 27
Ordering Information ...................................................... 28
Ordering Code Definitions ......................................... 28
Package Diagram ............................................................ 29
Acronyms ........................................................................ 30
Document Conventions ................................................. 30
Units of Measure ....................................................... 30
Document History Page ................................................. 31
Sales, Solutions, and Legal Information ...................... 33
Worldwide Sales and Design Support ....................... 33
Products .................................................................... 33
PSoC Solutions ......................................................... 33
Document Number: 38-05617 Rev. *I
Page 4 of 33
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CY7C1422AV18, CY7C1429AV18
CY7C1423AV18, CY7C1424AV18
Selection Guide
Description
Maximum Operating Frequency
Maximum Operating Current
×8
×9
×18
×36
300 MHz
300
825
845
880
980
278 MHz
278
775
775
815
890
250 MHz
250
700
700
740
800
200 MHz
200
600
600
600
665
167 MHz
167
500
500
500
560
Unit
MHz
mA
Document Number: 38-05617 Rev. *I
Page 5 of 33
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