CY7C1470V33
CY7C1472V33
CY7C1474V33
72-Mbit (2M × 36/4M × 18/1M × 72)
Pipelined SRAM with NoBL™ Architecture
72-Mbit (2M × 36/4M × 18/1M × 72) Pipelined SRAM with NoBL™ Architecture
Features
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Functional Description
The CY7C1470V33, CY7C1472V33, and CY7C1474V33 are
3.3 V, 2M × 36/4M × 18/1M × 72 synchronous pipelined burst
SRAMs with No Bus Latency™ (NoBL logic, respectively.
They are designed to support unlimited true back-to-back
read/write operations with no wait states. The CY7C1470V33,
CY7C1472V33, and CY7C1474V33 are equipped with the
advanced (NoBL) logic required to enable consecutive
read/write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of data
in systems that require frequent write/read transitions. The
CY7C1470V33, CY7C1472V33, and CY7C1474V33 are pin
compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. The clock
input is qualified by the clock enable (CEN) signal, which when
deasserted suspends operation and extends the previous clock
cycle.
Write operations are controlled by the byte write selects
(BW
a
–BW
h
for CY7C1474V33, BW
a
–BW
d
for CY7C1470V33
and BW
a
–BW
b
for CY7C1472V33) and a write enable (WE)
input. All writes are conducted with on-chip synchronous self
timed write circuitry.
Three synchronous chip enables (CE
1
, CE
2
, CE
3
) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. In order to avoid bus
contention, the output drivers are synchronously tristated during
the data portion of a write sequence.
For a complete list of related documentation, click
here.
Pin compatible and functionally equivalent to ZBT
Supports 200 MHz Bus operations with zero wait states
❐
Available speed grades are 200 and 167 MHz
Internally self timed output buffer control to eliminate the need
to use asynchronous OE
Fully registered (inputs and outputs) for pipelined operation
Byte write capability
Single 3.3 V power supply
3.3 V/2.5 V I/O power supply
Fast clock-to-output time
❐
3.0 ns (for 200 MHz device)
Clock enable (CEN) pin to suspend operation
Synchronous self timed writes
CY7C1470V33 available in JEDEC-standard Pb-free 100-pin
TQFP, and non Pb-free 165-ball FBGA package.
CY7C1472V33 available in JEDEC-standard Pb-free 100-pin
TQFP. CY7C1474V33 available in non Pb-free 209-ball FBGA
package
IEEE 1149.1 JTAG boundary scan compatible
Burst capability – linear or interleaved burst order
“ZZ” sleep mode option and stop clock option
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Selection Guide
Description
Maximum access time
Maximum operating current
Maximum CMOS standby current
200 MHz
3.0
500
120
167 MHz
3.4
450
120
Unit
ns
mA
mA
Errata:
For information on silicon errata, see
Errata on page 35.
Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-05289 Rev. *X
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 5, 2018
CY7C1470V33
CY7C1472V33
CY7C1474V33
Contents
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 8
Functional Overview ...................................................... 10
Single Read Accesses .............................................. 10
Burst Read Accesses ................................................ 10
Single Write Accesses ............................................... 10
Burst Write Accesses ................................................ 11
Sleep Mode ............................................................... 11
Interleaved Burst Address Table ............................... 11
Linear Burst Address Table ....................................... 11
ZZ Mode Electrical Characteristics ............................ 11
Truth Table ...................................................................... 12
Partial Write Cycle Description ..................................... 13
Partial Write Cycle Description ..................................... 13
Partial Write Cycle Description ..................................... 14
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 15
Disabling the JTAG Feature ...................................... 15
Test Access Port (TAP) ............................................. 15
PERFORMING A TAP RESET .................................. 15
TAP REGISTERS ...................................................... 15
TAP Instruction Set ................................................... 15
TAP Controller State Diagram ....................................... 17
TAP Controller Block Diagram ...................................... 18
TAP Timing Diagram ...................................................... 18
TAP AC Switching Characteristics ............................... 19
3.3 V TAP AC Test Conditions ....................................... 20
3.3 V TAP AC Output Load Equivalent ......................... 20
2.5 V TAP AC Test Conditions ....................................... 20
2.5 V TAP AC Output Load Equivalent ......................... 20
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 20
Identification Register Definitions ................................ 21
Scan Register Sizes ....................................................... 21
Identification Codes ....................................................... 21
Boundary Scan Exit Order ............................................. 22
Boundary Scan Exit Order ............................................. 23
Maximum Ratings ........................................................... 24
Operating Range ............................................................. 24
Neutron Soft Error Immunity ......................................... 24
Electrical Characteristics ............................................... 24
Capacitance .................................................................... 25
Thermal Resistance ........................................................ 25
AC Test Loads and Waveforms ..................................... 26
Switching Characteristics .............................................. 27
Switching Waveforms .................................................... 28
Ordering Information ...................................................... 30
Ordering Code Definitions ......................................... 30
Package Diagrams .......................................................... 31
Acronyms ........................................................................ 34
Document Conventions ................................................. 34
Units of Measure ....................................................... 34
Errata ............................................................................... 35
Part Numbers Affected .............................................. 35
Product Status ........................................................... 35
Ram9 NoBL ZZ Pin Issues Errata Summary ............. 35
Document History Page ................................................. 36
Sales, Solutions, and Legal Information ...................... 40
Worldwide Sales and Design Support ....................... 40
Products .................................................................... 40
PSoC® Solutions ...................................................... 40
Cypress Developer Community ................................. 40
Technical Support ..................................................... 40
Document Number: 38-05289 Rev. *X
Page 4 of 40
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