CY7C196) and three-state drivers. They have an automatic
power-down feature, reducing the power consumption by 75%
when deselected.
Writing to the device is accomplished when the Chip Enable(s)
(CE on the CY7C194 and CY7C195, CE
1
, CE
2
on the
CY7C196) and Write Enable (WE) inputs are both LOW. Data
on the four input pins (I/O
0
through I/O
3
) is written into the
memory location, specified on the address pins (A
0
through
A
15
).
Reading the device is accomplished by taking the Chip En-
able(s) (CE on the CY7C194 and CY7C195, CE
1
, CE
2
on the
CY7C196) LOW, while Write Enable (WE) remains HIGH. Un-
der these conditions the contents of the memory location
specified on the address pins will appear on the four data I/O
pins.
A die coat is used to ensure alpha immunity.
Functional Description
The CY7C194, CY7C195, and CY7C196 are high-perfor-
mance CMOS static RAMs organized as 65,536 by 4 bits.
Easy memory expansion is provided by active LOW Chip En-
Logic Block Diagram
Pin Configurations
DIP/SOJ
Top View
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
I/O
3
SENSE AMPS
I/O
2
I/O
1
I/O
0
CE
GND
1
2
3
4
5
6 7C194
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
A
5
A
4
A
3
A
2
A
1
A
0
I/O
3
I/O
2
I/O
1
I/O
0
WE
NC
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
CE
1
OE
GND
DIP/SOJ
Top View
1
2
3
4
5
6 7C195
7 7C196
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
A
5
A
4
A
3
A
2
A
1
A
0
NC
I/O
3
I/O
2
I/O
1
I/O
0
WE
C194-3
INPUT BUFFER
CE
2
(7C196)
NC
(7C195)
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
ROW DECODER
1024 x 64 x 4
ARRAY
C194-2
COLUMN
DECODER
POWER
DOWN
CE
2
(7C196 only)
CE
1
WE
(OE)
(7C195 and
7C196 ONLY)
C194-1
A
0
A
11
A
12
A
13
A
14
Selection Guide
7C194-12
7C195-12
7C196-12
12
155
30
7C194-15
7C195-15
7C196-15
15
145
30
7C194-20
7C195-20
7C196-20
20
135
30
7C194-25
7C195-25
7C196-25
25
115
30
7C194-35
7C195-35
7C196-35
35
115
30
7C194-45
7C196-45
45
30
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Cypress Semiconductor Corporation
Document #: 38-05162 Rev. **
A
15
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised September 18, 2001
CY7C194
CY7C195
CY7C196
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................–0.5V to V
CC
+ 0.5V
DC Input Voltage
[1]
................................–0.5V to V
CC
+ 0.5V
]
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Range
Commercial
Ambient
Temperature
[2]
0
°
C to +70
°
C
V
CC
5V
±
10%
Electrical Characteristics
Over the Operating Range
7C194-12
7C195-12
7C196-12
Parameter
V
OH
V
OL
V
IH
V
IL[1]
I
IX
I
OZ
I
OS
I
CC
I
SB1
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage
Current
Output Short
Circuit Current
[3]
V
CC
Operating
Supply Current
Automatic CE
Power-Down Current
—TTL Inputs
[4]
Automatic CE
Power-Down Current
—CMOS Inputs
[4]
GND < V
I
< V
CC
GND < V
O
< V
CC
,
Output Disabled
V
CC
= Max.,
V
OUT
= GND
V
CC
=Max., I
OUT
=0 mA,
f=f
MAX
=1/t
RC
Max. V
CC
, CE
1,2
> V
IH
,
V
IN
> V
IH
or V
IN
< V
IL
, f = f
MAX
Max. V
CC
, CE
1,2
> V
CC
- 0.3V,
V
IN
> V
CC
- 0.3V or
V
IN
< 0.3V, f = 0
Test Conditions
V
CC
= Min., I
OH
=
−4.0
mA
V
CC
= Min., I
OL
= 8.0 mA
2.2
−0.5
−5
−5
Min.
2.4
0.4
V
CC
+ 0.3V
0.8
+5
+5
−300
155
30
2.2
−0.5
−5
−5
Max.
7C194-15
7C195-15
7C196-15
Min.
2.4
0.4
V
CC
+ 0.3V
0.8
+5
+5
−300
145
30
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
I
SB2
10
10
mA
Notes:
1. Minimum voltage is equal to –2.0V for pulse durations of less than 20 ns.
2. T
A
is the “Instant On” case temperature.
3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
4. A pull-up resistor to V
CC
on the CE input is required to keep the device deselected during V
CC
power-up, otherwise I
SB
will exceed values given.
Document #: 38-05162 Rev. **
Page 2 of 12
CY7C194
CY7C195
CY7C196
)
Electrical Characteristics
Over the Operating Range (continued)
7C194-20
7C195-20
7C196-20
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage
Current
Output Short
Circuit Current
[3]
V
CC
Operating
Supply Current
Automatic CE
Power-Down Current
—TTL Inputs
[4]
Automatic CE
Power-Down Current
—CMOS Inputs
[4]
GND < V
I
< V
CC
GND < V
O
< V
CC
,
Output Disabled
V
CC
= Max.,
V
OUT
= GND
V
CC
=Max., I
OUT
=0 mA,
f=f
MAX
=1/t
RC
Max. V
CC
, CE
1,2
> V
IH
,
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
, CE
1,2
> V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V or
V
IN
< 0.3V, f = 0
Test Conditions
V
CC
= Min., I
OH
=
−4.0
mA
V
CC
= Min., I
OL
= 8.0 mA
2.2
–0.5
–5
–5
Min.
2.4
0.4
V
CC
+ 0.3V
0.8
+5
+5
–300
135
30
2.2
–0.5
–5
–5
Max.
7C194-25, 35, 45
7C195-25, 35
7C196-25, 35, 45
Min.
2.4
0.4
V
CC
+0.3V
0.8
+5
+5
–300
115
30
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
I
SB2
15
15
mA
Capacitance
[5]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
8
10
Unit
pF
pF
AC Test Loads and Waveforms
[6]
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
R2
255
Ω
R1 481
Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R2
255
Ω
C194-4
R1 481
Ω
ALL INPUT PULSES
3.0V
GND
10%
< t
r
90%
90%
10%
< t
r
C194-5
Equivalent to:
THÉ
EVENIN EQUIVALENT
167
Ω
OUTPUT
1.73V
Notes:
5. Tested initially and after any design or process changes that may affect these parameters.
6. t
r
= < 3 ns for the -12 and -15 speeds. T.
r
= < 5 ns for the -20 and slower speeds.
Document #: 38-05162 Rev. **
Page 3 of 12
CY7C194
CY7C195
CY7C196
:
Switching Characteristics
Over the Operating Range
[7]
7C194-12
7C195-12
7C196-12
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE1
,
t
ACE2
t
DOE
t
LZOE
t
HZOE
t
LZCE1
,
t
LZCE2
t
HZCE1
,
t
HZCE2
t
PU
t
PD
Read Cycle Time
Address to Data
Valid
Output Hold from
Address Change
CE LOW to
Data Valid
OE LOW to
Data Valid
OE LOW to
Low Z
OE HIGH to
High Z
[8]
CE LOW to
Low Z
[8]
CE HIGH to
High Z
[8,8]
CE LOW to
Power-Up
CE HIGH to
Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to
Write End
Address Hold from
Write End
Address Set-Up to
Write Start
WE Pulse Width
Data Set-Up to
Write End
Data Hold from
Write End
WE HIGH to
Low Z
[8]
WE LOW to
High Z
[8, 9]
12
9
9
0
0
8
8
0
3
7
0
12
7C195,
7C196
7C195,
7C196
7C195,
7C196
3
5
0
15
0
5
3
7
0
20
3
12
5
0
7
3
9
0
25
12
12
3
15
7
0
9
3
11
0
35
15
15
3
20
9
3
11
3
15
0
45
20
20
3
25
10
3
15
3
15
25
25
3
35
16
3
15
35
35
3
45
16
45
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C194-15
7C195-15
7C196-15
7C194-20
7C195-20
7C196-20
7C194-25
7C195-25
7C196-25
7C194-35
7C195-35
7C196-35
7C194-45
7C196-45
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
WRITE CYCLE
[10]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
15
10
10
0
0
9
9
0
3
7
20
15
15
0
0
15
10
0
3
10
25
18
20
0
0
18
10
0
3
0
13
35
22
25
0
0
22
15
0
3
0
15
45
22
35
0
0
22
15
0
3
0
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
7. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V,
input pulse levels of 0 to 3.0V, and output loading of the specified I
OL
/I
OH
and 30-pF load capacitance.
8. t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
9. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
and t
HZWE
is less than t
LZWE
for any given device.
10. The internal write time of the memory is defined by the overlap of CE
1
LOW, CE
2
LOW, and WE LOW. All signals must be LOW to initiate a write and any signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05162 Rev. **
Page 4 of 12
CY7C194
CY7C195
CY7C196
Switching Waveforms
Read Cycle No. 1
[11, 12]
t
RC
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID
t
AA
DATA VALID
C194-8
Read Cycle No. 2
CE
1
, CE
2
[11, 13]
t
RC
t
ACE
OE
(7C195 and
7C196)
t
DOE
t
LZOE
HIGH IMPEDANCE
t
LZCE
t
HZOE
t
HZCE
DATA VALID
t
PD
HIGH
IMPEDANCE
DATA OUT
V
CC
SUPPLY
CURRENT
t
PU
50%
ICC
50%
ISB
C194-6
Write Cycle No. 1 (CE Controlled)
[10, 14, 15]
t
WC
ADDRESS
CE
1
CE
2
(7C196)
t
SCE
t
SA
t
AW
t
HA
WE
t
SD
DATA I/O
DATA VALID
C194-7
t
HD
Notes:
11. WE is HIGH for read cycle.
12. Device is continuously selected: CE
1
= V
IL
, CE
2
= V
IL
(7C196), and OE = V
IL
(7C195 and 7C196).
13. Address valid prior to or coincident with CE
1
and CE
2
transition LOW.
14. Data I/O will be high impedance if OE = V
IH
(7C195 and 7C196).
15. If any CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
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