Latch-Up Current.................................................... > 200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0
°
C to +70
°
C
−40
°
C to +85
°
C
V
CC
5V
±
10%
5V
±
10%
Document #: 38-06033 Rev. *A
Page 2 of 24
CY7C451
CY7C453
CY7C454
Pin Definitions
Signal
Name
D
0 – 8
I/O
I
Description
Data Inputs: When the FIFO is not full and ENW is active, CKW (rising edge) writes data (D
0 – 8
) into
the FIFO’s memory. If MR is asserted at the rising edge of CKW then data is written into the FIFO’s
programming register. D
8
is ignored if the device is configured for parity generation.
Data Outputs: When the FIFO is not empty and ENR is active, CKR (rising edge) reads data (Q
0 – 7
)
out of the FIFO’s memory. If MR is active at the rising edge of CKR then data is read from the
programming register.
Function varies according to mode:
Parity disabled - same function as Q
0 – 7
Parity enabled, generation - parity generation bit (PG)
Parity enabled, check - Parity Error Flag (PE)
Enable Write: enables the CKW input (for both non-program and program modes)
Enable Read: enables the CKR input (for both non-program and program modes)
Write Clock: the rising edge clocks data into the FIFO when ENW is LOW; updates Half Full, Almost
Full, and Full flag states. When MR is asserted, CKW writes data into the program register.
Read Clock: the rising edge clocks data out of the FIFO when ENR is LOW; updates the Empty and
Almost Empty flag states. When MR is asserted, CKR reads data out of the program register.
Half Full Flag - synchronized to CKW.
Empty or Full Flag - E is synchronized to CKR; F is synchronized to CKW
Dual-Mode Pin:
Not Cascaded - Programmable Almost Full is synchronized to CKW; Programmable Almost Empty is
synchronized to CKR
Cascaded - Expansion Out signal, connected to XI of next device
Not Cascaded - XI is tied to V
SS
Cascaded - Expansion Input, connected to XO of previous device
First Load/ Retransmit Pin:
Cascaded - the first device in the daisy chain will have FL tied to V
SS
; all other devices will have FL
tied to V
CC
(Figure
2)
Not Cascaded - tied to V
CC;
Retransmit function is also available in stand alone mode by strobing RT
Master Reset: resets device to empty condition.
Non-Programming Mode: program register is reset to default condition of no parity and PAFE active at
16 or less locations from Full/Empty.
Programming Mode: Data present on D
0 – 8
is written into the programmable register on the rising
edge of CKW. Program register contents appear on Q
0 – 8
after the rising edge of CKR.
Output Enable for Q
0 – 7
and Q
8
/PG/PE pins
Q
0 – 7
O
Q
8
/PG/PE
O
ENW
ENR
CKW
CKR
HF
E/F
PAFE/XO
I
I
I
I
O
O
O
XI
FL/RT
I
I
MR
I
OE
I
Document #: 38-06033 Rev. *A
Page 3 of 24
CY7C451
CY7C453
CY7C454
Electrical Characteristics
Over the Operating Range
7C451-12
7C453-12
7C454-12
Parameter
V
OH
V
OL
V
IH[2]
V
IL
I
IX
I
OS[3]
I
OZL
I
OZH
I
CC1[4]
I
CC2[5]
I
SB[6]
[2]
7C451-14
7C453-14
7C454-14
2.4
7C451-20
7C453-20
7C454-20
2.4
7C451-30
7C453-30
7C454-30
2.4
V
0.4
2.2
−0.5
−10
−90
V
CC
0.8
+10
V
V
V
µA
mA
+10
100
110
70
80
30
30
µA
mA
mA
mA
mA
mA
mA
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Current
Output Short
Circuit Current
Output OFF, High Z
Current
Operating Current
Operating Current
Standby Current
Test Conditions
V
CC
= Min., I
OH
=
−2.0
mA
V
CC
= Min., I
OL
= 8.0 mA
Min. Max. Min. Max. Min. Max. Min. Max. Unit
2.4
0.4
2.2
−0.5
V
CC
0.8
+10
2.2
−0.5
−10
−90
+10
140
150
70
80
30
30
−10
+10
140
150
70
80
30
30
0.4
V
CC
0.8
+10
2.2
−0.5
−10
−90
−10
0.4
V
CC
0.8
+10
V
CC
= Max.
V
CC
= Max., V
OUT
= GND
OE > V
IH
, V
SS
< V
O
< V
CC
V
CC
= Max.,
I
OUT
= 0 mA
V
CC
= Max.,
I
OUT
= 0 mA
V
CC
= Max.,
I
OUT
= 0 mA
Com’l
Mil/Ind
Com’l
Mil/Ind
Com’l
Mil/Ind
−10
−90
−10
+10
120
130
70
80
30
30
−10
Capacitance
[7]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25
°
C, f = 1 MHz,
V
CC
= 5.0V
Max.
10
12
Unit
pF
pF
Notes:
2. The V
IH
and V
IL
specifications apply for all inputs except XI. The XI pin is not a TTL input. It is connected to either XO of the previous device or V
SS
.
3. Test no more than one output at a time for not more than one second.
4. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at maximum frequency (f
MAX
), while data inputs
switch at f
MAX
/2. Outputs are unloaded.
5. Input signals switch from 0V to 3V with a rise/fall time less than 3 ns, clocks and clock enables switch at 20 MHz, while the data inputs switch at 10 MHz.
Outputs are unloaded.
6. All input signals are connected to V
CC
. All outputs are unloaded. Read and write clocks switch at maximum frequency (f
MAX
).
7. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-06033 Rev. *A
Page 4 of 24
CY7C451
CY7C453
CY7C454
AC Test Loads and Waveforms
[8, 9, 10, 11, 12]
R1500Ω
5V
OUTPUT
C
L
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
200Ω
OUTPUT
2V
R2
333Ω
3.0V
GND
< 3 ns
ALL INPUT PULSES
90%
10%
90%
10%
< 3 ns
C451-5
C451-4
Switching Characteristics
Over the Operating Range
[13]
7C451-12
7C453-12
7C454-12
Parameter
t
CKW
t
CKR
t
CKH
t
CKL
t
A[14]
t
OH
t
FH
t
SD
t
HD
t
SEN
t
HEN
t
OE
t
OLZ[7,15]
t
OHZ[7,15]
t
PG
t
PE
t
FD
t
SKEW1
[16]
7C451-14
7C453-14
7C454-14
Min.
14
14
6.5
6.5
Max.
7C451-20
7C453-20
7C454-20
Min.
20
20
9
9
Max.
7C451-30
7C453-30
7C454-30
Min.
30
30
12
12
Max.
Unit
ns
ns
ns
ns
20
0
0
7
0
7
0
ns
ns
ns
ns
ns
ns
ns
20
0
20
20
20
20
0
ns
ns
ns
ns
ns
ns
ns
Description
Write Clock Cycle
Read Clock Cycle
Clock HIGH
Clock LOW
Data Access Time
Previous Output Data Hold After Read HIGH
Previous Flag Hold After Read/Write HIGH
Data Set-Up
Data Hold
Enable Set-Up
Enable Hold
OE LOW to Output Data Valid
OE LOW to Output Data in Low Z
OE HIGH to Output Data in High Z
Read HIGH to Parity Generation
Read HIGH to Parity Error Flag
Flag Delay
Opposite Clock After Clock
Min.
12
12
5
5
Max.
9
0
0
4
0
4
0
9
0
9
9
9
9
0
0
0
0
0
5
0
5
0
10
0
0
6
0
6
0
10
0
10
10
10
10
0
15
15
15
15
15
15
Notes:
8. C
L
= 30 pF for all AC parameters except for t
OHZ
.
9. C
L
= 5 pF for t
OHZ
.
10. All AC measurements are referenced to 1.5V except t
OE
, t
OLZ
, and t
OHZ
.
11. t
OE
and t
OLZ
are measured at
±
100 mV from the steady state.
12. t
OHZ
is measured at +500 mV from V
OL
and – 500 mV from V
OH
.
13. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and output loading as shown in AC Test Loads and Waveforms
and capacitance as in notes 8 and 9, unless otherwise specified.
14. Access time includes all data outputs switching simultaneously.
15. At any given temperature and voltage condition, t
OLZ
is greater than t
OHZ
for any given device.
16. t
SKEW1
is the minimum time an opposite clock can occur after a clock and still be guaranteed not to be included in the current clock cycle (for purposes
of flag update). If the opposite clock occurs less than t
SKEW1
after the clock, the decision of whether or not to include the opposite clock in the current
clock cycle is arbitrary.
Note:
The opposite clock is the signal to which a flag is not synchronized; i.e., CKW is the opposite clock for Empty and Almost
Empty flags, CKR is the opposite clock for the Almost Full, Half Full, and Full flags. The clock is the signal to which a flag is synchronized; i.e., CKW is the
clock for the Half Full, Almost Full, and Full flags, CKR is the clock for Empty and Almost Empty flags.
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