IDTCSPT857D
2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
2.5V - 2.6V PHASE LOCKED
LOOP DIFFERENTIAL 1:10
SDRAM CLOCK DRIVER
FEATURES:
DESCRIPTION:
IDTCSPT857D
• 1 to 10 differential clock distribution
• Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications requiring improved output crosspoint
voltage
• Operating frequency: 60MHz to 220MHz
• Very low skew:
– <100ps for PC1600 - PC2700
– <75ps for PC3200
• Very low jitter:
– <75ps for PC1600 - PC2700
– <50ps for PC3200
• 2.5V AV
DD
and 2.5V V
DDQ
for PC1600-PC2700
• 2.6V AV
DD
and 2.6V V
DDQ
for PC3200
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Available in 48-pin TSSOP and TVSOP, 40-pin VFQFPN, and 56-
pin VFBGA packages
The CSPT857D is a PLL based clock driver that acts as a zero delay buffer
to distribute one differential clock input pair(CLK,
CLK
) to 10 differential output
pairs (Y
[0:9]
, Y
[0:9]
) and one differential pair of feedback clock output (FBOUT,
FBOUT).
External feedback pins (FBIN,
FBIN)
for synchronization of the
outputs to the input reference is provided. A CMOS Enable/Disable pin is
available for low power disable. When the input frequency falls below
approximately 20MHz, the device will enter power down mode. In this mode,
the receivers are disabled, the PLL is turned off, and the output clock drivers
are tristated, resulting in a current consumption of less than 200µA.
The CSPT857D requires no external components and has been optimised
for very low I/O phase error, skew, and jitter, while maintaining frequency and
duty cycle over the operating voltage and temperature range. The CSPT857D,
designed for use in both module assemblies and system motherboard based
solutions, provides an optimum high-performance clock source.
The CSPT857D is available in Commercial Temperature Range (0°C to
+70°C) and Industrial Temperature Range (-40°C to +85°C). See Ordering
Information for details.
APPLICATIONS:
• Meets or exceeds JEDEC standard JESD 82-1A for registered
DDR clock driver
• Meets proposed DDR1-400 specification
• For all DDR1 speeds: PC1600 (DDR200), PC2100 (DDR266),
PC2700 (DDR333), PC3200 (DDR400)
• Along with SSTV16857, SSTVF16857, SSTV16859, SSTVM16859,
SSTVF16859, SSTVN16859, DDR1 register, provides complete
solution for DDR1 DIMMs
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c
2003
Integrated Device Technology, Inc.
OCTOBER 2003
DSC-6835/3
IDTCSPT857D
2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FUNCTIONAL BLOCK DIAGRAM
PWRDWN
TEST
MODE
LOGIC
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
CLK
CLK
FBIN
FBIN
PLL
Y5
Y5
Y6
Y6
Y7
Y7
Y8
Y8
Y9
Y9
FBOUT
FBOUT
AV
DD
2
IDTCSPT857D
2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
PWR
DWN
6
Y
5
Y
5
Y
6
Y
6
GND
GND
NC
NC
GND
GND
C
Y
7
Y
7
NC
NC
Y
2
Y
2
D
FBIN
V
DDQ
FBOUT
Y
8
Y
8
Y
9
Y
9
5
V
DDQ
FBIN FBOUT GND
NC
NC
V
DDQ
V
DDQ
E
4
GND V
DDQ
GND V
DDQ
Y
0
Y
0
A
NC
NC
V
DDQ
GND
V
DDQ
GND
Y
3
Y
3
J
3
2
Y
1
Y
1
B
CLK
CLK
F
AV
DD
GND
V
DDQ
AGND
G
H
Y
4
Y
4
K
1
VFBGA
TOP VIEW
56 BALL VFBGA PACKAGE LAYOUT
0.65mm
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
TOP VIEW
A
1
2
3
4
5
6
B
C
D
E
F
G
H
J
K
3
IDTCSPT857D
2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
V
DDQ
V
DDQ
GND
Y
6
Y
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
Y
5
Y
5
V
DDQ
Y
6
Y
6
GND
GND
Y
7
Y
7
V
DDQ
PWRDWN
FBIN
FBIN
V
DDQ
FBOUT
FBOUT
GND
Y
8
Y
8
V
DDQ
Y
9
Y
9
GND
Y
1
Y
1
Y
0
Y
0
Y
5
Y
5
Y
0
Y
0
30
29
28
27
26
25
24
23
22
21
Y
7
Y
7
V
DDQ
PWRDWN
FBIN
FBIN
V
DDQ
40
GND
Y
2
Y
2
V
DDQ
CLK
CLK
V
DDQ
AV
DD
AGND
GND
1
2
3
4
5
6
7
8
9
10
11
39
38
37
36
35
34
33
32
31
V
DDQ
Y
1
Y
1
GND
GND
Y
2
Y
2
GND
V
DDQ
FBOUT
FBOUT
V
DDQ
V
DDQ
CLK
CLK
V
DDQ
AV
DD
AGND
12
13
14
15
16
17
18
19
20
V
DDQ
V
DDQ
Y
3
Y
3
Y
4
Y
4
Y
9
Y
9
Y
8
VFQFPN
TOP VIEW
Y
8
GND
Y
3
Y
3
Unit
V
V
V
mA
mA
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
DDQ
, AV
DD
V
I(2)
V
O(2)
I
IK
(V
I
<0)
I
OK
(V
O
<0 or
V
O
> V
DDQ
)
I
O
Rating
Supply Voltage Range
Input Voltage Range
Voltage range applied to any
output in the high or low state
Input Clamp Current
Output Clamp Current
Max
–0.5 to +3.6
–0.5 to V
DDQ
+ 0.5
–0.5 to V
DDQ
+ 0.5
–50
±50
V
DDQ
Y
4
Y
4
GND
TSSOP/ TVSOP
TOP VIEW
Continuous Output Current
±50
±100
– 65 to +150
mA
mA
°C
(V
O
=0 to V
DDQ
)
V
DDQ
or GND
Continuous Current
TSTG
Storage Temperature Range
CAPACITANCE
(1)
Parameter
C
IN
C
I(∆)
C
L
Description
Input Capacitance
V
I
= V
DDQ
or GND
Delta Input Capacitance
V
I
= V
DDQ
or GND
Load Capacitance
—
14
—
pF
NOTE:
1. Unused inputs must be held high or low to prevent them from floating.
Min.
2.5
-0.25
Typ.
—
—
Max.
3.5
0.25
Unit
pF
pF
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
of 150
°
C and a board trace length of 750 mils.
4
IDTCSPT857D
2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
RECOMMENDED OPERATING CONDITIONS
Symbol
AV
DD
V
DDQ
T
A
Supply Voltage
I/O Supply Voltage
PC1600-PC2700
PC3200
Operating Free-Air Temperature
Parameter
Min.
V
DDQ
– 0.12
2.3
2.5
-40
Typ.
V
DDQ
2.5
2.6
Max.
2.7
2.7
2.7
+85
Unit
V
V
°
C
PIN DESCRIPTION (TSSOP/TVSOP)
Pin Name
AGND
AV
DD
CLK,
CLK
FBIN,
FBIN
FBOUT,
FBOUT
GND
PWRDWN
V
DDQ
Y
[0:9]
Y
[0:9]
Pin Number
17
16
13, 14
35, 36
32, 33
1, 7, 8, 18, 24, 25, 31, 41, 42, 48
37
4, 11, 12, 15, 21, 28, 34, 38, 45
3, 5, 10, 20, 22, 27, 29, 39, 44, 46
2, 6, 9, 19, 23, 26, 30, 40, 43, 47
Ground for analog supply
Analog supply
Differential clock input
Feedback differential clock input
Feedback differential clock output
Ground
Output enable for Y and
Y
I/O supply
Buffered output of input clock, CLK
Buffered output of input clock,
CLK
Description
PIN DESCRIPTION (VFBGA)
Pin Name
AGND
AV
DD
CLK,
CLK
FBIN,
FBIN
FBOUT,
FBOUT
GND
PWRDWN
V
DDQ
Y
[0:9]
Y
[0:9]
Pin Number
H1
G2
F1, F2
F5, F6
H6, G5
A3, A4, C1, C2, C5, C6, H2, H5, K3, K4
E6
B3, B4, E1, E2, E5, G1, G6, J3, J4
A1, A6, B2, B5, D1, D6, J2, J5, K1, K6
A2, A5, B1, B6, D2, D5, J1, J6, K2, K5
Ground for analog supply
Analog supply
Differential clock input
Feedback differential clock input
Feedback differential clock output
Ground
Output enable for Y and
Y
I/O supply
Buffered output of input clock, CLK
Buffered output of input clock,
CLK
Description
PIN DESCRIPTION (VFQFPN)
Pin Name
AGND
AV
DD
CLK,
CLK
FBIN,
FBIN
FBOUT,
FBOUT
GND
PWRDWN
V
DDQ
Y
[0:9]
Y
[0:9]
Pin Number
9
8
5, 6
25, 26
21, 22
1, 10
27
4, 7, 13, 18, 23, 24, 28, 33, 38
3, 12, 14, 17, 19, 29, 32, 34, 37, 39
2, 11, 15, 16, 20, 30, 31, 35, 36, 40
Ground for analog supply
Analog supply
Differential clock input
Feedback differential clock input
Feedback differential clock output
Ground
Output enable for Y and
Y
I/O supply
Buffered output of input clock, CLK
Buffered output of input clock,
CLK
Description
5
FPGA/CPLD
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