nRF52840
Objective
Product Specification
v0.5
Key features
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Bluetooth 5 ready multiprotocol radio
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Bluetooth 5
data rate support: 2 Mbs, 1Mbs, 500 kbs, 125 kbs
32-bit
ARM
®
Cortex
®
-M4F
@
64 MHz
High speed 2 Mbs data rate
104 dB link budget for Bluetooth low energy
Full-speed 12 Mbs USB controller
NFC-A tag on-chip
Software stacks available as downloads
Application development independent of protocol stacks
Programmable output power from +8 dBm to -20 dBm
-96 dBm Sensitivity for Bluetooth low energy
ARM
®
TrustZone®
Cryptocell
310 cryptographic accelerator
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Applications
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Advanced wearables
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Connected watches
Advanced personal fitness devices
Wearables with wireless payment
Connected health
Virtual/Augmented Reality applications
Smart home sensors and controllers
Industrial IoT sensors and controllers
Advanced
Remote controls
Gaming controllers
Internet of Things (IoT)
Interactive entertainment devices
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On-air compatible with
nRF52,
nRF51, nRF24L, and nRF24AP Series
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RSSI
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Wide supply voltage range +5.5 v to 1.7 v
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Full selection of interfaces SPI/UART/PWM
• Programmable peripheral interconnect (PPI)
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High speed SPI interface 32 MHz
• Quad
SPI interface 32 MHz
• EasyDMA
for all digital interfaces
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RAM mapped FIFO using
EasyDMA
12 bit /200K SPS ADC
I28
bit AES/ECB/CCM/AAR co-processor
Single-ended antenna output (on-chip balun)
On-chip DC-DC buck converter
Quadrature demodulator
Individual power management for all peripherals
Regulated supply for external components up to 25 mA
All rights reserved.
Reproduction in whole or in part is prohibited without the prior written permission of the copyright holder.
2016-12-05
Contents
Contents
1 Revision history................................................................................... 9
2 About this document............................................................................................ 10
2.1 Peripheral naming and abbreviations................................................................................... 10
2.2 Register tables...................................................................................................................... 10
2.3 Registers............................................................................................................................... 11
3 Block diagram........................................................................................................12
4 Pin assignments.................................................................................................... 13
4.1 QIAA pin assignments.......................................................................................................... 13
5 Absolute maximum ratings.................................................................................. 16
6 Recommended operating conditions.................................................................. 17
7 CPU......................................................................................................................... 18
7.1 Floating point interrupt.......................................................................................................... 18
7.2 Electrical specification........................................................................................................... 18
7.3 CPU and support module configuration................................................................................19
8 Memory................................................................................................................... 20
8.1
8.2
8.3
8.4
RAM - Random access memory...........................................................................................20
Flash - Non-volatile memory.................................................................................................20
Memory map......................................................................................................................... 21
Instantiation........................................................................................................................... 23
9 AHB multilayer.......................................................................................................25
10 EasyDMA.............................................................................................................. 26
10.1 EasyDMA array list............................................................................................................. 27
11 NVMC — Non-volatile memory controller......................................................... 28
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
Writing to flash.................................................................................................................... 28
Erasing a page in flash.......................................................................................................28
Writing to user information configuration registers (UICR)................................................. 28
Erasing user information configuration registers (UICR).................................................... 28
Erase all.............................................................................................................................. 29
Cache.................................................................................................................................. 29
Registers............................................................................................................................. 29
Electrical specification......................................................................................................... 32
12 FICR — Factory information configuration registers.......................................33
12.1 Registers............................................................................................................................. 33
13 UICR — User information configuration registers........................................... 44
13.1 Registers............................................................................................................................. 44
14 Peripheral interface............................................................................................. 58
14.1
14.2
14.3
14.4
14.5
14.6
14.7
14.8
15.1
15.2
15.3
15.4
Peripheral ID....................................................................................................................... 58
Peripherals with shared ID..................................................................................................58
Peripheral registers............................................................................................................. 59
Bit set and clear..................................................................................................................59
Tasks................................................................................................................................... 59
Events..................................................................................................................................60
Shortcuts............................................................................................................................. 60
Interrupts............................................................................................................................. 60
DAP - Debug Access Port.................................................................................................. 62
CTRL-AP - Control Access Port......................................................................................... 63
Debug interface mode.........................................................................................................65
Real-time debug.................................................................................................................. 65
15 Debug and trace.................................................................................................. 62
Page 2
Contents
15.5 Trace................................................................................................................................... 65
16 POWER — Power supply....................................................................................67
16.1 Main supply......................................................................................................................... 67
16.2 USB supply......................................................................................................................... 72
16.3 System OFF mode..............................................................................................................73
16.4 System ON mode............................................................................................................... 74
16.5 RAM power control............................................................................................................. 74
16.6 Reset................................................................................................................................... 74
16.7 Retained registers............................................................................................................... 75
16.8 Reset behavior.................................................................................................................... 75
16.9 Registers............................................................................................................................. 76
16.10 Electrical specification..................................................................................................... 139
17 CLOCK — Clock control...................................................................................142
17.1
17.2
17.3
17.4
HFCLK clock controller..................................................................................................... 142
LFCLK clock controller......................................................................................................144
Registers........................................................................................................................... 146
Electrical specification....................................................................................................... 150
18 Power and clock management.........................................................................153
18.1 Current consumption scenarios........................................................................................ 153
19 GPIO — General purpose input/output........................................................... 155
19.1
19.2
19.3
19.4
20.1
20.2
20.3
20.4
20.5
Pin configuration............................................................................................................... 155
GPIO located near the RADIO......................................................................................... 157
Registers........................................................................................................................... 157
Electrical specification....................................................................................................... 198
Pin events and tasks........................................................................................................ 201
Port event..........................................................................................................................202
Tasks and events pin configuration.................................................................................. 202
Registers........................................................................................................................... 202
Electrical specification....................................................................................................... 211
20 GPIOTE — GPIO tasks and events..................................................................201
21 PPI — Programmable peripheral interconnect............................................... 212
21.1 Pre-programmed channels................................................................................................213
21.2 Registers........................................................................................................................... 213
22 RADIO — 2.4 GHz Radio.................................................................................. 249
22.1 Packet configuration..........................................................................................................249
22.2 Address configuration........................................................................................................250
22.3 Data whitening.................................................................................................................. 251
22.4 CRC...................................................................................................................................251
22.5 Radio states...................................................................................................................... 252
22.6 Transmit sequence............................................................................................................252
22.7 Receive sequence.............................................................................................................254
22.8 Received Signal Strength Indicator (RSSI).......................................................................255
22.9 Interframe spacing.............................................................................................................255
22.10 Device address match.................................................................................................... 256
22.11 Bit counter....................................................................................................................... 256
22.12 IEEE 802.15.4 Operation................................................................................................ 257
22.13 EasyDMA.........................................................................................................................264
22.14 Registers......................................................................................................................... 265
22.15 Electrical specification..................................................................................................... 286
23 TIMER — Timer/counter....................................................................................290
23.1
23.2
23.3
23.4
23.5
23.6
Capture..............................................................................................................................291
Compare............................................................................................................................291
Task delays....................................................................................................................... 291
Task priority.......................................................................................................................291
Registers........................................................................................................................... 291
Electrical specification....................................................................................................... 297
24 RTC — Real-time counter.................................................................................298
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Contents
24.1 Clock source..................................................................................................................... 298
24.2 Resolution versus overflow and the PRESCALER........................................................... 298
24.3 COUNTER register............................................................................................................299
24.4 Overflow features.............................................................................................................. 299
24.5 TICK event........................................................................................................................ 299
24.6 Event control feature.........................................................................................................300
24.7 Compare feature............................................................................................................... 300
24.8 TASK and EVENT jitter/delay........................................................................................... 302
24.9 Reading the COUNTER register.......................................................................................304
24.10 Registers......................................................................................................................... 304
24.11 Electrical specification..................................................................................................... 310
25 RNG — Random number generator................................................................ 311
25.1
25.2
25.3
25.4
Bias correction.................................................................................................................. 311
Speed................................................................................................................................ 311
Registers........................................................................................................................... 311
Electrical specification....................................................................................................... 313
26 TEMP — Temperature sensor.......................................................................... 314
26.1 Registers........................................................................................................................... 314
26.2 Electrical specification....................................................................................................... 319
27 ECB — AES electronic codebook mode encryption...................................... 320
27.1
27.2
27.3
27.4
27.5
Shared resources.............................................................................................................. 320
EasyDMA...........................................................................................................................320
ECB data structure............................................................................................................320
Registers........................................................................................................................... 321
Electrical specification....................................................................................................... 322
28 CCM — AES CCM mode encryption................................................................323
28.1 Shared resources.............................................................................................................. 323
28.2 Key-steam generatioin...................................................................................................... 323
28.3 Encryption..........................................................................................................................324
28.4 Decryption......................................................................................................................... 324
28.5 AES CCM and RADIO concurrent operation.................................................................... 325
28.6 Encrypting packets on-the-fly in radio transmit mode.......................................................325
28.7 Decrypting packets on-the-fly in radio receive mode........................................................326
28.8 CCM data structure...........................................................................................................327
28.9 EasyDMA and ERROR event........................................................................................... 328
28.10 Registers......................................................................................................................... 328
28.11 Electrical specification..................................................................................................... 332
29 AAR — Accelerated address resolver.............................................................333
29.1 Shared resources.............................................................................................................. 333
29.2 EasyDMA...........................................................................................................................333
29.3 Resolving a resolvable address........................................................................................333
29.4 Use case example for chaining RADIO packet reception with address resolution using
AAR.......................................................................................................................................334
29.5 IRK data structure............................................................................................................. 334
29.6 Registers........................................................................................................................... 335
29.7 Electrical specification....................................................................................................... 337
30 SPIM — Serial peripheral interface master with EasyDMA............................338
30.1
30.2
30.3
30.4
30.5
30.6
30.7
SPI master transaction sequence..................................................................................... 338
Pin configuration............................................................................................................... 339
Shared resources.............................................................................................................. 340
EasyDMA...........................................................................................................................340
Low power.........................................................................................................................341
Registers........................................................................................................................... 341
Electrical specification....................................................................................................... 349
31 SPIS — Serial peripheral interface slave with EasyDMA...............................351
31.1 Shared resources.............................................................................................................. 351
31.2 EasyDMA...........................................................................................................................351
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Contents
31.3
31.4
31.5
31.6
SPI slave operation...........................................................................................................352
Pin configuration............................................................................................................... 353
Registers........................................................................................................................... 354
Electrical specification....................................................................................................... 362
2
32 TWIM — I C compatible two-wire interface master with EasyDMA...............364
32.1 Shared resources.............................................................................................................. 365
32.2 EasyDMA...........................................................................................................................365
32.3 Master write sequence......................................................................................................365
32.4 Master read sequence...................................................................................................... 366
32.5 Master repeated start sequence....................................................................................... 367
32.6 Low power.........................................................................................................................368
32.7 Master mode pin configuration......................................................................................... 368
32.8 Registers........................................................................................................................... 368
32.9 Electrical specification....................................................................................................... 375
32.10 Pullup resistor................................................................................................................. 376
33 TWIS — I C compatible two-wire interface slave with EasyDMA.................. 377
33.1 Shared resources.............................................................................................................. 379
33.2 EasyDMA...........................................................................................................................379
33.3 TWI slave responding to a read command.......................................................................379
33.4 TWI slave responding to a write command...................................................................... 380
33.5 Master repeated start sequence....................................................................................... 381
33.6 Terminating an ongoing TWI transaction..........................................................................382
33.7 Low power.........................................................................................................................382
33.8 Slave mode pin configuration........................................................................................... 382
33.9 Registers........................................................................................................................... 383
33.10 Electrical specification..................................................................................................... 389
2
34 UARTE — Universal asynchronous receiver/transmitter with EasyDMA.... 391
34.1 Shared resources.............................................................................................................. 391
34.2 EasyDMA...........................................................................................................................391
34.3 Transmission..................................................................................................................... 392
34.4 Reception.......................................................................................................................... 392
34.5 Error conditions................................................................................................................. 394
34.6 Using the UARTE without flow control............................................................................. 394
34.7 Parity and stop bit configuration....................................................................................... 394
34.8 Low power.........................................................................................................................395
34.9 Pin configuration............................................................................................................... 395
34.10 Registers......................................................................................................................... 395
34.11 Electrical specification..................................................................................................... 404
35 QDEC — Quadrature decoder.......................................................................... 405
35.1
35.2
35.3
35.4
35.5
35.6
35.7
35.8
Sampling and decoding.................................................................................................... 405
LED output........................................................................................................................ 406
Debounce filters................................................................................................................ 406
Accumulators.....................................................................................................................407
Output/input pins............................................................................................................... 407
Pin configuration............................................................................................................... 407
Registers........................................................................................................................... 408
Electrical specification....................................................................................................... 414
36 SAADC — Successive approximation analog-to-digital converter............... 415
36.1 Shared resources.............................................................................................................. 415
36.2 Overview............................................................................................................................415
36.3 Digital output..................................................................................................................... 416
36.4 Analog inputs and channels..............................................................................................417
36.5 Operation modes...............................................................................................................417
36.6 EasyDMA...........................................................................................................................419
36.7 Resistor ladder.................................................................................................................. 420
36.8 Reference.......................................................................................................................... 421
36.9 Acquisition time................................................................................................................. 421
36.10 Limits event monitoring................................................................................................... 422
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