The Si6926AEDQ is a dual N-Channel MOSFET with ESD
protection and gate over-voltage protection circuitry
incorporated into the MOSFET. The device is designed for
use in Lithium Ion battery pack circuits. The 2-stage input
protection circuit is a unique design, consisting of two stages
of back-to-back zener diodes separated by a resistor. The
first stage diode is designed to absorb most of the ESD
energy. The second stage diode is designed to protect the
gate from any remaining ESD energy and over-voltages
above the gates inherent safe operating range. The series
resistor used to limit the current through the second stage
diode during over voltage conditions has a maximum value
which limits the input current to
≤
10 mA at 14 V and the
maximum t
off
to 15 µs. The Si6926AEDQ has been
optimized as a battery or load switch in Lithium Ion
applications with the advantage of both a 2.5 V R
DS(on)
rating
and a safe 14 V gate-to-source maximum rating.
APPLICATION CIRCUITS
D
ESD and
Overvoltage
Protection
ESD and
Overvoltage
Protection
R*
G
S
*R typical value is 1.9 kΩ by design.
Battery Protection Circuit
See Typical Characteristics,
Gate-Current vs. Gate-Source Voltage, Page 3.
Figure 1. Typical Use In a Lithium Ion Battery Pack
Figure 2. Input ESD and Overvoltage Protection Circuit
Document Number: 73090
S-81056-Rev. B, 12-May-08
www.vishay.com
1
Si6926AEDQ
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
D
1
D
2
TSSOP-8
D
1
S
1
S
1
G
1
1
2
3
4
Top View
Ordering Information:
Si6926AEDQ-T1-GE3 (Lead (Pb)-free and Halogen-free)
S
1
N-Channel
N-Channel
S
2
8 D
2
7 S
2
6 S
2
5 G
2
1.8 kΩ
G
1
G
2
1.8 kΩ
Figure 3.
Figure 4.
ABSOLUTE MAXIMUM RATINGS
T
A
= 25 °C, unless otherwise noted
Parameter
Drain-Source Voltage, Source-Drain Voltage
Gate-Source Voltage
Continuous Drain-to-Source Current (T
J
= 150 °C)
a
Pulsed Drain-to-Source Current
Pulsed Source Current (Diode Conduction)
a
Maximum Power Dissipation
a
Operating Junction and Storage Temperature Range
T
A
= 25 °C
T
A
= 70 °C
T
A
= 25 °C
T
A
= 70 °C
Symbol
V
DS
V
GS
I
D
I
DM
I
S
P
D
T
J
, T
stg
0.83
1.0
0.64
- 55 to 150
4.5
3.6
20
0.69
0.83
0.53
W
°C
10 s
20
± 14
4.1
3.3
A
Steady State
Unit
V
THERMAL RESISTANCE RATINGS
Parameter
Maximum Junction-to-Ambient
a
Maximum Junction-to-Foot (Drain)
Notes:
a. Surface Mounted on FR4 board.
t
≤
10 s
Steady State
Steady State
Symbol
R
thJA
R
thJF
Typical
90
126
65
Maximum
125
150
80
°C/W
Unit
www.vishay.com
2
Document Number: 73090
S-81056-Rev. B, 12-May-08
Si6926AEDQ
Vishay Siliconix
SPECIFICATIONS
T
J
= 25 °C, unless otherwise noted
Parameter
Static
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Current
b
Drain-Source On-State Resistance
b
Forward Transconductance
b
Diode Forward Voltage
b
Dynamic
a
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
V
DD
= 10 V, R
L
= 10
Ω
I
D
≅
1 A, V
GEN
= 4.5 V, R
g
= 6
Ω
V
DS
= 10 V, V
GS
= 4.5 V, I
D
= 4.5 A
7.6
1.5
1.5
0.43
0.8
5.0
2.5
0.7
1.2
7.5
4.0
µs
12
nC
V
GS(th)
I
GSS
I
DSS
I
D(on)
R
DS(on)
g
fs
V
SD
V
DS
= V
GS
, I
D
= 250 µA
V
DS
= 0 V, V
GS
= ± 4.5 V
V
DS
= 0 V, V
GS
= ± 12 V
V
DS
= 20 V, V
GS
= 0 V
V
DS
= 20 V, V
GS
= 0 V, T
J
= 55 °C
V
DS
≥
5 V, V
GS
= 5 V
V
GS
=
4.5 V, I
D
= 4.5 A
V
GS
= 3.0 V, I
D
= 4.2 A
V
GS
= 2.5 V, I
D
= 3.9 A
V
DS
= 10 V, I
D
= 4.5 A
I
S
= 0.83 A, V
GS
= 0 V
10
0.023
0.025
0.027
26
0.65
1.1
0.030
0.033
0.035
S
V
Ω
0.4
1.2
±1
± 10
1
5
V
µA
mA
µA
A
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Notes:
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width
≤
300 µs, duty cycle
≤
2 %.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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