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74LVX573M_Q

产品描述Latches Octal Latch
产品类别半导体    逻辑   
文件大小91KB,共7页
制造商ON Semiconductor(安森美)
官网地址http://www.onsemi.cn
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74LVX573M_Q概述

Latches Octal Latch

74LVX573M_Q规格参数

参数名称属性值
Product AttributeAttribute Value
制造商
Manufacturer
ON Semiconductor(安森美)
产品种类
Product Category
Latches
RoHSN
Number of Circuits8 Circuit
Logic TypeLatch
Logic Family74L
PolarityNon-Inverting
Quiescent Current4 uA
Number of Output Lines3 Line
High Level Output Current- 4 mA
传播延迟时间
Propagation Delay Time
18 ns at 2.7 V, 12.8 ns at 3.3 V
电源电压-最大
Supply Voltage - Max
3.6 V
电源电压-最小
Supply Voltage - Min
2 V
最小工作温度
Minimum Operating Temperature
- 40 C
最大工作温度
Maximum Operating Temperature
+ 85 C
封装 / 箱体
Package / Case
SOIC-20
系列
Packaging
Tube
FunctionTransparent
高度
Height
2.35 mm
长度
Length
13 mm
输出类型
Output Type
3-State
类型
Type
D-Type
宽度
Width
7.6 mm
安装风格
Mounting Style
SMD/SMT
Number of Channels8 Channels
Number of Input Lines8 Line
工作电源电压
Operating Supply Voltage
2 V to 3.6 V
Reset TypeNo Reset
单位重量
Unit Weight
0.028254 oz

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74LVX573 Low Voltage Octal Latch with 3-STATE Outputs
June 1993
Revised April 2005
74LVX573
Low Voltage Octal Latch with 3-STATE Outputs
General Description
The LVX573 is a high-speed octal latch with buffered com-
mon Latch Enable (LE) and buffered common Output
Enable (OE) inputs. The LVX573 is functionally identical to
the LVX373 but with inputs and outputs on opposite sides
of the package. The inputs tolerate up to 7V allowing inter-
face of 5V systems to 3V systems.
Features
s
Input voltage translation from 5V to 3V
s
Ideal for low power/low noise 3.3V applications
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Ordering Code:
Order Number
74LVX573M
74LVX573SJ
74LVX573MTC
Package Number
M20B
M20D
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Latch Outputs
Description
© 2005 Fairchild Semiconductor Corporation
DS011616
www.fairchildsemi.com

 
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