D ts e t
aa h e
R c e t r lc r nc
o h se Ee to is
Ma u a t r dCo o e t
n fc u e
mp n n s
R c e tr b a d d c mp n ns ae
o h se rn e
o oet r
ma ua trd u ig ete dewaes
n fcue sn i r i/ fr
h
p rh s d f m te oiia s p l r
uc a e r
o h r n l u pi s
g
e
o R c e tr waes rce td f m
r o h se
fr e rae r
o
te oiia I. Al rce t n ae
h
r nl P
g
l e rai s r
o
d n wi tea p o a o teOC
o e t h p rv l f h
h
M.
P r aetse u igoiia fcoy
at r e td sn r n la tr
s
g
ts p o rmso R c e tr e eo e
e t rga
r o h se d v lp d
ts s lt n t g aa te p o u t
e t oui s o u rne
o
rd c
me t o e c e teOC d t s e t
es r x e d h
M aa h e.
Qu l yOv riw
ai
t
e ve
• IO- 0 1
S 90
•A 92 cr ct n
S 1 0 et ai
i
o
• Qu l e Ma ua trr Ls (
ai d
n fcues it QML MI- R -
) LP F
385
53
•C a sQ Mitr
ls
lay
i
•C a sVS a eL v l
ls
p c ee
• Qu l e S p l r Ls o D sr uos( L )
ai d u pi s it f it b tr QS D
e
i
•R c e trsacic l u pir oD A a d
o h se i
r ia s p l t L n
t
e
me t aln u t a dD A sa d r s
es lid sr n L tn ad .
y
R c e tr lcrnc , L i c mmi e t
o h se Ee t is L C s o
o
tdo
t
s p ligp o u t ta s t f c so r x e t-
u pyn rd cs h t ai y u tme e p ca
s
t n fr u lya daee u loto eoiial
i s o q ai n r q a t h s r n l
o
t
g
y
s p l db id sr ma ua trr.
u pi
e yn ut
y n fcues
T eoiia ma ua trr d ts e t c o a yn ti d c me t e e t tep r r n e
h r n l n fcue’ aa h e a c mp n ig hs o u n r cs h ef ma c
g
s
o
a ds e ic t n o teR c e tr n fcue v rino ti d vc . o h se Ee t n
n p c ai s f h o h se ma ua trd eso f hs e ie R c e tr lcr -
o
o
isg aa te tep r r n eo i s mio d co p o u t t teoiia OE s e ic -
c u rne s h ef ma c ft e c n u tr rd cs o h r n l M p c a
o
s
g
t n .T pc lv le aefr eee c p r o e o l. eti mii m o ma i m rt g
i s ‘y ia’ au s r o rfrn e up s s ny C r n nmu
o
a
r xmu ai s
n
ma b b s do p o u t h rceiain d sg , i lt n o s mpetsig
y e a e n rd c c aa tr t , e in smuai , r a l e t .
z o
o
n
© 2 1 R cetr l t n s LC Al i t R sre 0 1 2 1
0 3 ohs E cr i , L . lRg s eevd 7 1 0 3
e e oc
h
T l r m r, l s v iw wrcl . m
o e n oe p ae it w . e c o
a
e
s
o ec
www.ti.com
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E
−
AUGUST 1995
−
REVISED SEPTEMBER 2010
HIGH-SPEED PWM CONTROLLER
FEATURES
D
Improved Versions of the UC3823/UC3825
D
D
D
D
DESCRIPTION
The UC3823A and UC3823B and the UC3825A and
UC3825B family of PWM controllers are improved
versions of the standard UC3823 and UC3825 family.
Performance enhancements have been made to several
of the circuit blocks. Error amplifier gain bandwidth product
is 12 MHz, while input offset voltage is 2 mV. Current limit
threshold is assured to a tolerance of 5%. Oscillator
discharge current is specified at 10 mA for accurate dead
time control. Frequency accuracy is improved to 6%.
Startup supply current, typically 100
μA,
is ideal for off-line
applications. The output drivers are redesigned to actively
sink current during UVLO at no expense to the startup
current specification. In addition each output is capable of
2-A peak currents during transitions.
D
D
Low 100-μA Startup Current
D
Pulse-by-Pulse Current Limiting Comparator
D
Latched Overcurrent Comparator With Full
Cycle Restart
PWMs
Compatible with Voltage-Mode or
Current-Mode Control Methods
Practical Operation at Switching Frequencies
to 1 MHz
50-ns Propagation Delay to Output
High-Current Dual Totem Pole Outputs
(2-A Peak)
Trimmed Oscillator Discharge Current
BLOCK DIAGRAM
CLK/LEB 4
RT 5
OSC
CT 6
RAMP 7
EAOUT 3
NI
2
E/A
INV 1
1.25 V
(60%)
*
R
SD
PWM
LATCH
T
13 VC
11 OUTA
14 OUTB
12 PGND
9
mA
PWM COMPARATOR
SOFT−START COMPLETE
SS 8
ILIM 9
1.2 V
0.2 V
VCC 15
GND 10
”B” 16V/10V
”A” 9.2V/8.4V
RESTART
DELAY
CURRENT
LIMIT
1.0 V
OVER CURRENT
SD
R
FAULT LATCH
UVLO
VREF
5.1 V
ON/OFF
INTERNAL
BIAS
16 5.1 VREF
UDG−02091
5V
RESTART
DELAY
LATCH
S
R
250
mA
4V
V
REF
GOOD
* On the UC1823A version, toggles Q and Q are always low.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright
©
2004
−2008,
Texas Instruments Incorporated
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E
−
AUGUST 1995
−
REVISED SEPTEMBER 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
Functional improvements have also been implemented in this family. The UC3825 shutdown comparator is now a
high-speed overcurrent comparator with a threshold of 1.2 V. The overcurrent comparator sets a latch that ensures full
discharge of the soft-start capacitor before allowing a restart. While the fault latch is set, the outputs are in the low state.
In the event of continuous faults, the soft-start capacitor is fully charged before discharge to insure that the fault frequency
does not exceed the designed soft start period. The UC3825 CLOCK pin has become CLK/LEB. This pin combines the
functions of clock output and leading edge blanking adjustment and has been buffered for easier interfacing.
The UC3825A and UC3825B have dual alternating outputs and the same pin configuration of the UC3825. The UC3823A
and UC3823B outputs operate in phase with duty cycles from zero to less than 100%. The pin configuration of the UC3823A
and UC3823B is the same as the UC3823 except pin 11 is now an output pin instead of the reference pin to the current
limit comparator. “A” version parts have UVLO thresholds identical to the original UC3823 and UC3825. The “B” versions
have UVLO thresholds of 16 V and 10 V, intended for ease of use in off-line applications.
Consult the application note,
The UC3823A,B and UC3825A,B Enhanced Generation of PWM Controllers,
(SLUA125) for
detailed technical and applications information.
ORDERING INFORMATION
UVLO
T
A
MAXIMUM
DUTY CYCLE
< 100%
< 50%
< 100%
< 50%
9.2 V / 8.4 V
SOIC−16
(1)
(DW)
−40°C
to 85°C
40°C
−0°C
to 70°C
0°C
(1)
16 V / 10 V
PLCC−20
(1)
(Q)
UC2823AQ
UC2825AQ
UC3823AQ
UC3825AQ
SOIC−16
(DW)
UC2823BDW
UC2825BDW
UC3823BDW
UC3825BDW
PDIP−16
(N)
UC2823BN
UC2825BN
UC3823BN
UC3825BN
PLCC−20
(1)
(Q)
−
−
−
UC3825BQ
PDIP−16
(N)
UC2823AN
UC2825AN
UC3823AN
UC3825AN
UC2823ADW
UC2825ADW
UC3823ADW
UC3825ADW
The DW and Q packages are also available taped and reeled. Add TR suffix to the device type (i.e., UC2823ADWR). To order quantities of 1000
devices per reel for the Q package and 2000 devices per reel for the DW package.
UVLO
T
A
MAXIMUM
DUTY CYCLE
< 100%
< 50%
9.2 V / 8.4 V
CDIP−16
(J)
UC1823AJ, UC1823AJ883B, UC1823AJQMLV
UC1825AJ, UC1825AJ883B, UC1825AJQMLV
LCCC−20
(L)
UC1823AL, UC1823AL883B
UC1825AL, UC1825AL883B, UC1825ALQMLV
−55°C
to 125°C
55°C
PIN ASSIGNMENTS
DW, J, OR N PACKAGES
(TOP VIEW)
Q OR L PACKAGES
(TOP VIEW)
INV
NI
EAOUT
CLK/LEB
RT
CT
RAMP
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VREF
VCC
OUTB
VC
PGND
OUTA
GND
ILIM
NI
INV
NC
VREF
VCC
EAOUT
CLK/LEB
NC
RT
CT
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
OUTB
VC
NC
PGND
OUTA
NC = no connection
2
RAMP
SS
NC
ILIM
GND
www.ti.com
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E
−
AUGUST 1995
−
REVISED SEPTEMBER 2010
TERMINAL FUNCTIONS
NAME
CLK/LEB
CT
EAOUT
GND
ILIM
INV
NI
OUTA
OUTB
PGND
RAMP
RT
SS
VC
VCC
VREF
TERMINAL
NO.
J or DW
Q or L
4
5
6
3
10
9
1
2
11
14
12
7
5
8
13
15
16
8
4
13
12
2
3
14
18
15
9
7
10
17
19
20
I/O
O
I
O
−
I
I
I
O
O
−
I
I
I
−
−
O
DESCRIPTION
Output of the internal oscillator
Timing capacitor connection pin for oscillator frequency programming. The timing capacitor should
be connected to the device ground using minimal trace length.
Output of the error amplifier for compensation
Analog ground return pin
Input to the current limit comparator
Inverting input to the error amplifier
Non-inverting input to the error amplifier
High current totem pole output A of the on-chip drive stage.
High current totem pole output B of the on-chip drive stage.
Ground return pin for the output driver stage
Non-inverting input to the PWM comparator with 1.25-V internal input offset. In voltage mode
operation, this serves as the input voltage feed-forward function by using the CT ramp. In peak
current mode operation, this serves as the slope compensation input.
Timing resistor connection pin for oscillator frequency programming
Soft-start input pin which also doubles as the maximum duty cycle clamp.
Power supply pin for the output stage. This pin should be bypassed with a 0.1-μF monolithic ceramic
low ESL capacitor with minimal trace lengths.
Power supply pin for the device. This pin should be bypassed with a 0.1-μF monolithic ceramic low
ESL capacitor with minimal trace lengths
5.1-V reference. For stability, the reference should be bypassed with a 0.1-μF monolithic ceramic
low ESL capacitor and minimal trace length to the ground plane.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
UNIT
V
IN
I
O
I
O
Supply voltage,
Source or sink current, DC
Source or sink current, pulse (0.5
μs)
Analog inputs
Power ground
Outputs
I
CLK
I
O(EA)
I
SS
I
OSC
T
J
T
stg
t
STG
Clock output current
Error amplifier output current
Soft-start sink current
Oscillator charging current
Storage temperature
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
Storage temperature
Lead temperature 1,6 mm (1/16 inch) from cases for 10 seconds
(1)
VC, VCC
OUTA, OUTB
OUTA, OUTB
INV, NI, RAMP
ILIM, SS
PGND
OUTA, OUTB limits
CLK/LEB
EAOUT
SS
RT
22 V
0.5 A
2.2 A
−0.3
V to 7 V
−0.3
V to 6 V
±0.2
V
PGND
−0.3
V to V
C
+0.3 V
−5
mA
5 mA
20 mA
−5
mA
−55°C
to 150°C
−65°C
to 150°C
−55C°C
to 150°C
−65°C
to 150°C
300°C
Operating virtual junction temperature range
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
3
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E
−
AUGUST 1995
−
REVISED SEPTEMBER 2010
www.ti.com
ELECTRICAL CHARACTERISTICS
T
A
=
−55°C
to 125°C for the UC1823A/UC1825A, T
A
=
−40°C
to 85°C for the UC2823x/UC2825x, T
A
= 0°C to 70°C for the UC3823x/UC3825x,
R
T
= 3.65 kΩ, C
T
= 1 nF, V
CC
= 12 V, T
A
= T
J
(unless otherwise noted)
PARAMETER
REFERENCE, V
REF
V
O
Ouput voltage range
Line regulation
Load regulation
Total output variation
Temperature stability
(1)
Output noise
voltage
(1)
Long term stability
(1)
Short circuit current
OSCILLATOR
f
OSC
Initial accuracy
(1)
Total variation
(1)
Voltage stability
Temperature stability
(1)
High-level output voltage, clock
Low-level output voltage, clock
Ramp peak
Ramp valley
Ramp valley-to-peak
I
OSC
Oscillator discharge current
Input offset voltage
Input bias current
Input offset current
Open loop gain
CMRR
PSRR
I
O(sink)
I
O(src)
Common mode rejection ratio
Power supply rejection ratio
Output sink current
Output source current
High-level output voltage
Low-level output voltage
Gain bandwidth product
Slew
(1)
TEST CONDITIONS
T
J
= 25°C,
I
O
= 1 mA
MIN
5.05
TYP
5.1
2
5
MAX
5.15
15
20
5.17
0.4
25
90
425
1.1
450
1.15
1%
UNIT
V
mV
V
mV/°C
μV
RMS
mV
mA
kHz
MHz
kHz
MHz
12 V
≤
VCC
≤
20 V
1 mA
≤
I
O
≤
10 mA
Line, load, temperature
T
(min)
< T
A
< T
(max)
10 Hz < f < 10 kHz
T
J
= 125°C,
VREF = 0 V
T
J
= 25°C
R
T
= 6.6 kΩ, C
T
= 220 pF, T
A
= 25°C
Line, temperature
R
T
= 6.6 kΩ, C
T
= 220 pF,
12 V < VCC < 20 V
T
(min)
< T
A
< T
(max)
+/−
3.7
2.6
0.7
1.6
R
T
= OPEN,
V
CT
= 2 V
9
1000 hours
30
375
0.9
350
0.85
5.03
0.2
50
5
60
400
1
5%
4
0
2.8
1
1.8
10
2
0.6
0.1
0.2
3
1.25
2
11
10
3
1
mA
mV
μA
A
V
ERROR AMPLIFIER
1 V < V
O
< 4 V
1.5 V < V
CM
< 5.5 V
12 V < V
CC
< 20 V
V
EAOUT
= 1 V
V
EAOUT
= 4 V
I
EAOUT
=
−0.5
mA
I
EAOUT
=
−1
mA
f = 200 kHz
60
75
85
1
4.5
0
6
6
95
95
110
2.5
−1.3
4.7
0.5
12
9
−0.5
5
1
mA
V
Mhz
V/μs
dB
rate
(1)
Ensured by design. Not production tested.
4
51单片机
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
