TC74ACT174P/F/FN
TOSHIBA CMOS Digital Integrated Circuit
Silicon Monolithic
TC74ACT174P,TC74ACT174F,TC74ACT174FN
Hex D-Type Flip Flop with Clear
Note:
xxxFN (JEDEC SOP) is not available in
Japan.
The TC74ACT174 is an advanced high speed CMOS HEX
D-TYPE FLIP FLOP fabricated with silicon gate and
double-layer metal wiring C
2
MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
This device may be used as a level converter for interfacing
TTL or NMOS to High Speed CMOS. The inputs are compatible
with TTL, NMOS and CMOS output voltage levels.
Information signals applied to D inputs are transferred to the
Q outputs on the positive going edge of the clock pulse.
When the
CLR
input is held low, the Q output are in the low
logic level independent of the other inputs.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
TC74ACT174P
TC74ACT174F
Features
•
•
•
•
High speed: f
max
=
155 MHz (typ.) at V
CC
=
5 V
Low power dissipation: I
CC
=
8
μA
(max) at Ta
=
25°C
Compatible with TTL outputs: V
IL
=
0.8 V (max)
V
IH
=
2.0 V (min)
Symmetrical output impedance: |I
OH
|
=
I
OL
=
24 mA (min)
Capability of driving 50
Ω
•
•
transmission lines.
Balanced propagation delays: t
pLH
∼
t
pHL
−
Pin and function compatible with 74F174
Weight
DIP16-P-300-2.54A
SOP16-P-300-1.27A
SOL16-P-150-1.27
TC74ACT174FN
Pin Assignment
: 1.00 g (typ.)
: 0.18 g (typ.)
: 0.13 g (typ.)
1
2007-10-01
TC74ACT174P/F/FN
IEC Logic Symbol
Truth Table
Inputs
CLR
Output
CK
X
Q
L
L
H
Q
n
D
X
L
H
X
Function
Clear
⎯
⎯
No Change
L
H
H
H
X: Don’t care
System Diagram
2
2007-10-01
TC74ACT174P/F/FN
Absolute Maximum Ratings (Note 1)
Characteristics
Supply voltage range
DC input voltage
DC output voltage
Input diode current
Output diode current
DC output current
DC V
CC
/ground current
Power dissipation
Storage temperature
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
P
D
T
stg
Rating
−0.5
to 7.0
−0.5
to V
CC
+
0.5
−0.5
to V
CC
+
0.5
±20
±50
±50
±150
500 (DIP) (Note 2)/180 (SOP)
−65
to 150
Unit
V
V
V
mA
mA
mA
mA
mW
°C
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 2: 500 mW in the range of Ta
= −40
to 65°C. From Ta
=
65 to 85°C a derating factor of
−10
mW/°C should be
applied up to 300 mW.
Operating Ranges (Note)
Characteristics
Supply voltage
Input voltage
Output voltage
Operating temperature
Input rise and fall time
Symbol
V
CC
V
IN
V
OUT
T
opr
dt/dV
Rating
4.5 to 5.5
0 to V
CC
0 to V
CC
−40
to 85
0 to 10
Unit
V
V
V
°C
ns/V
Note:
The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either VCC or GND.
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2007-10-01
TC74ACT174P/F/FN
Electrical Characteristics
DC Characteristics
Test Condition
Characteristics
Symbol
V
CC
(V)
⎯
⎯
I
OH
= −50 μA
V
IN
=
V
IH
or I
OH
= −24
mA
V
IL
I
OH
= −75
mA
I
OL
=
50
μA
V
IN
=
V
IH
or I
OL
=
24 mA
V
IL
I
OL
=
75 mA
V
IN
=
V
CC
or GND
V
IN
=
V
CC
or GND
Per input: V
IN
=
3.4 V
Other input: V
CC
or GND
4.5 to
5.5
4.5 to
5.5
4.5
4.5
(Note)
5.5
4.5
4.5
(Note)
5.5
5.5
5.5
5.5
Min
2.0
⎯
4.4
3.94
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Ta
=
25°C
Typ.
⎯
⎯
4.5
⎯
⎯
0.0
⎯
⎯
⎯
⎯
⎯
Max
⎯
0.8
⎯
⎯
⎯
0.1
0.36
⎯
±0.1
8.0
1.35
Ta
= −40
to
85°C
Min
2.0
⎯
4.4
3.80
3.85
⎯
⎯
⎯
⎯
⎯
⎯
Max
⎯
0.8
⎯
⎯
⎯
0.1
0.44
1.65
±1.0
80.0
1.5
μA
μA
mA
V
V
V
V
Unit
High-level input
voltage
Low-level input
voltage
High-level output
voltage
V
IH
V
IL
V
OH
Low-level output
voltage
Input leakage
current
Quiescent supply
current
V
OL
I
IN
I
CC
I
C
Note:
This spec indicates the capability of driving 50
Ω
transmission lines.
One output should be tested at a time for a 10 ms maximum duration.
Timing Requirements
(input: t
r
=
t
f
=
3 ns)
Characteristics
Symbol
Test Condition
V
CC
(V)
Minimum pulse width
(CK)
Minimum pulse width
(
CLR )
t
W (L)
t
W (H)
⎯
5.0
±
0.5
Ta
=
25°C
Limit
5.0
Ta
=
−40
to
85°C
Limit
5.0
ns
Unit
t
W (L)
t
s
t
h
t
rem
⎯
⎯
⎯
⎯
5.0
±
0.5
5.0
±
0.5
5.0
±
0.5
5.0
±
0.5
5.0
3.5
2.0
3.0
5.0
3.5
2.0
3.0
ns
ns
ns
ns
Minimum set-up time
Minimum hold time
Minimum removal time
( CLR )
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2007-10-01
TC74ACT174P/F/FN
AC Characteristics
(C
L
=
50 pF, R
L
=
500
Ω,
input: t
r
=
t
f
=
3 ns)
Characteristics
Propagation delay
time
(CK-Q)
Propagation delay
time
(
CLR
-Q)
Maximum clock
frequency
Input capacitance
Power dissipation
capacitance
f
max
C
IN
C
PD
(Note)
⎯
⎯
⎯
Symbol
Test Condition
V
CC
(V)
Min
⎯
Ta
=
25°C
Typ.
7.1
Max
10.1
Ta
= −
40 to
85°C
Min
1.0
Max
11.5
Unit
t
pLH
t
pHL
⎯
5.0
±
0.5
ns
t
pHL
⎯
5.0
±
0.5
⎯
7.4
11.8
1.0
13.5
ns
5.0
±
0.5
85
⎯
⎯
140
5
32
⎯
85
⎯
⎯
⎯
MHz
pF
pF
10
⎯
10
⎯
Note:
C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
I
CC (opr)
=
C
PD
½V
CC
½f
IN
+
I
CC
/6 (per F/F)
And the total C
PD
when n pcs of Flip Flop operate can be gained by the following equation.
C
PD
(total)
=
20
+
12½n
5
2007-10-01
FPGA/CPLD
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