74LVC06A
Hex inverter with open-drain outputs
Rev. 7 — 4 August 2020
Product data sheet
1. General description
The 74LVC06A provides six inverting buffers. The outputs are open-drain and can be connected to
other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices
as translators in mixed 3.3 V and 5 V applications.
2. Features and benefits
•
•
•
•
•
5 V tolerant inputs and outputs (open-drain) for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Complies with JEDEC standard:
•
JESD8-7A (1.65 V to 1.95 V)
•
JESD8-5A (2.3 V to 2.7 V)
•
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
•
HBM JESD22-A114F exceeds 2000 V
•
MM JESD22-A115-B exceeds 200 V
•
CDM JESD22-C101E exceeds 1000 V
Specified from -40 °C to +85 °C and -40 °C to +125 °C
•
•
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range
74LVC06AD
74LVC06APW
74LVC06ABQ
-40 °C to +125 °C
-40 °C to +125 °C
-40 °C to +125 °C
Name
SO14
TSSOP14
Description
plastic small outline package; 14 leads;
body width 3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT402-1
DHVQFN14 plastic dual in-line compatible thermal enhanced
SOT762-1
very thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
Nexperia
74LVC06A
Hex inverter with open-drain outputs
4. Functional diagram
1 1A
3 2A
5 3A
1Y 2
2Y 4
3Y 6
1A
1
1
1
1
1
1
1
mna526
2
1Y
2A
3
4
2Y
3A
5
6
3Y
9 4A
4Y 8
4A
9
8
4Y
11 5A
5Y 10
5A
11
10
5Y
Y
A
mna527
13 6A
6Y 12
6A
mna525
13
12
6Y
GND
Fig. 1.
Logic symbol
Fig. 2.
IEC logic symbol
Fig. 3.
Logic diagram for one gate
5. Pinning information
5.1. Pinning
74LVC06A
terminal 1
index area
14 V
CC
1A
2
3
4
5
6
7
GND
4Y
8
GND
(1)
1
74LVC06A
1A
1Y
2A
2Y
3A
3Y
GND
1
2
3
4
5
6
7
001aac916
1Y
14 V
CC
13 6A
12 6Y
11 5A
10 5Y
9
8
4A
4Y
13 6A
12 6Y
11 5A
10 5Y
9
4A
2A
2Y
3A
3Y
001aae245
Transparent top view
Fig. 4.
Pin configuration SOT108-1 (SO14)
and SOT402-1 (TSSOP14)
(1) This is not a ground pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to GND.
Fig. 5.
Pin configuration SOT762-1 (DHVQFN14)
5.2. Pin description
Table 2. Pin description
Symbol
1A, 2A, 3A, 4A, 5A, 6A
1Y, 2Y, 3Y, 4Y, 5Y, 6Y
GND
V
CC
Pin
1, 3, 5, 9, 11, 13
2, 4, 6, 8, 10, 12
7
14
Description
data input
data output
ground (0 V)
supply voltage
74LVC06A
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 7 — 4 August 2020
2 / 12
Nexperia
74LVC06A
Hex inverter with open-drain outputs
6. Functional description
Table 3. Function selection
H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state
Input
nA
L
H
Output
nY
Z
L
7. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Conditions
V
I
< 0
[1]
V
O
< 0
active mode
high-impedance mode
V
O
= 0 V to V
CC
[2]
[2]
Min
-0.5
-50
-0.5
-50
-0.5
-0.5
-
-
-100
-65
Max
+6.5
-
+6.5
-
+6.5
+6.5
50
100
-
+150
500
Unit
V
mA
V
mA
V
V
mA
mA
mA
°C
mW
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
T
amb
= -40 °C to +125 °C
[3]
-
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
For SOT108-1 (SO14) package: P
tot
derates linearly with 10.1 mW/K above 100 °C.
For SOT402-1 (TSSOP14) package: P
tot
derates linearly with 7.3 mW/K above 81 °C.
For SOT762-1 (DHVQFN14) package: P
tot
derates linearly with 9.6 mW/K above 98 °C.
8. Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter
V
CC
V
I
V
O
T
amb
Δt/ΔV
supply voltage
functional
input voltage
output voltage
ambient temperature
input transition rise and fall rate
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 5.5 V
active mode
high-impedance mode
Conditions
Min
1.65
1.2
0
0
0
-40
0
0
Typ
-
-
-
-
-
-
-
-
Max
5.5
-
5.5
5.5
5.5
+125
20
10
Unit
V
V
V
V
V
°C
ns/V
ns/V
74LVC06A
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 7 — 4 August 2020
3 / 12
Nexperia
74LVC06A
Hex inverter with open-drain outputs
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
Conditions
Min
HIGH-level input V
CC
= 1.2 V
voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
IL
LOW-level input V
CC
= 1.2 V
voltage
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
I
O
= 100 μA;
V
CC
= 1.65 V to 5.5 V
I
O
= 4 mA; V
CC
= 1.65 V
I
O
= 8 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 24 mA; V
CC
= 3.0 V
I
O
= 32 mA; V
CC
= 4.5 V
I
I
I
OZ
I
OFF
I
CC
ΔI
CC
input leakage
current
OFF-state
output current
V
I
= 5.5 V or GND;
V
CC
= 1.65 V to 5.5 V
V
I
= V
IH
; V
O
= 5.5 V or GND;
V
CC
= 1.65 V to 5.5 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
±0.1
±0.1
±0.1
0.1
5
0.20
0.45
0.3
0.4
0.55
0.55
±5
±10
±10
10
500
-
-
-
-
-
-
-
-
-
-
-
0.3
0.6
0.75
0.6
0.8
0.8
±20
±20
±20
40
5000
V
V
V
V
V
V
μA
μA
μA
μA
μA
1.08
0.65 × V
CC
1.7
2.0
0.7 × V
CC
-
-
-
-
-
-40 °C to +85 °C
Typ
[1]
-
-
-
-
-
-
-
-
-
-
Max
-
-
-
-
-
0.12
0.35 × V
CC
0.7
0.8
0.30 × V
CC
-40 °C to +125 °C
Min
1.08
0.65 × V
CC
1.7
2.0
0.7 × V
CC
-
-
-
-
-
Max
-
-
-
-
-
0.12
0.7
0.8
V
V
V
V
V
V
V
V
Unit
0.35 × V
CC
V
0.30 × V
CC
V
power-off
V
I
or V
O
= 5.5 V; V
CC
= 0 V
leakage current
supply current
additional
supply current
input
capacitance
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
per input pin;
V
I
= V
CC
- 0.6 V; I
O
= 0 A;
V
CC
= 2.7 V to 5.5 V
V
CC
= 0 V to 5.5 V;
V
I
= GND to V
CC
C
I
[1]
-
5.0
-
-
-
pF
All typical values are measured at V
CC
= 3.3 V (unless stated otherwise) and T
amb
= 25 °C.
74LVC06A
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 7 — 4 August 2020
4 / 12
Nexperia
74LVC06A
Hex inverter with open-drain outputs
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see
Fig. 7.
Symbol Parameter
t
PZL
OFF-state to LOW
propagation delay
Conditions
Min
nA to nY; see
Fig. 6
V
CC
= 1.2 V
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
t
PLZ
LOW to OFF-state
propagation delay
nA to nY; see
Fig. 6
V
CC
= 1.2 V
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V
V
CC
= 3.0 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
C
PD
power dissipation
capacitance
per buffer; V
I
= GND to V
CC
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3.0 V to 3.6 V
[1]
[2]
-40 °C to +85 °C
Typ
[1]
9
2.8
1.9
1.8
1.8
1.5
10
2.6
1.4
2.6
2.2
1.5
6.5
6.9
7.2
Max
-
5.7
3.1
3.9
3.7
2.5
-
5.7
3.1
3.9
3.7
2.6
-
-
-
-40 °C to +125 °C Unit
Min
-
0.5
0.5
0.5
0.5
0.7
-
0.5
0.5
0.5
0.5
0.6
-
-
-
Max
-
6.7
4.0
5.0
5.0
3.5
-
6.7
4.0
5.0
5.0
3.5
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
pF
pF
-
0.5
0.5
0.5
0.5
0.7
-
0.5
0.5
0.5
0.5
0.6
[2]
-
-
-
Typical values are measured at T
amb
= 25 °C and V
CC
= 1.2 V, 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
C
PD
is used to determine the dynamic power dissipation (P
D
in μW).
2
2
P
D
= C
PD
× V
CC
× f
i
× N + Σ(C
L
× V
CC
× f
o
) where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in Volts
N = number of inputs switching
2
Σ(C
L
× V
CC
× f
o
) = sum of the outputs
10.1. Waveforms and test circuit
V
I
nA input
GND
t
PLZ
V
CC
nY output
V
OL
V
X
mna529
V
M
t
PZL
V
M
Measurement points are given in
Table 8
Logic level: V
OL
is a typical output voltage level that occurs with the output load.
Fig. 6.
The input nA to output nY propagation delays
74LVC06A
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2020. All rights reserved
Product data sheet
Rev. 7 — 4 August 2020
5 / 12
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