AK5340-VS (1/3)
IL08
C-MOS 18-BIT 2 CHANNEL A/D CONVERTER
—TOP VIEW—
1
AINL
+
AINL
_
AINR
+
AINR
_
V REF IN
SEL18
PD
CLK
CMODE
SMODE
TST1
TST2
TST3
TST4
SCLK
FSYNC
L/R
15
17
14
V REF
SDATA
26
16
AINL
+
IN
1
AINL
_
IN
2
V REF
IN
3
4 AV
DD
5 AGND
6 NC
7 NC
TST1
IN/OUT
8
SEL18
IN
9
PD
IN
10
TST2
IN
11
CMODE
IN
12
SMODE
IN
13
L/
R
IN/OUT
14
28 AINR
+
IN
27 AINR
_
IN
26 V REF
OUT
NC 25
DV
DD
24
NC 23
22 TST4
IN
21 TST3
IN/OUT
20 CLK
IN
DGND 19
DV
DD
18
17 FSYNC
IN/OUT
16 SDATA
OUT
15 SCLK
IN/OUT
2
28
27
3
9
10
20
12
13
8
11
21
22
AV
DD
, AGND : FOR ANALOG BLOCK
DV
DD
, DGND : FOR DIGITAL BLOCK
AK5340-VS (2/3)
INPUT
AINL
+
AINL
_
AINR
+
AINR
_
CLK
CMODE
L-CH ANALOG POSITIVE INPUT
L-CH ANALOG NEGATIVE INPUT
R-CH ANALOG POSITIVE INPUT
R-CH ANALOG NEGATIVE INPUT
MASTER CLOCK
(CMODE = H : 384 fs)
(CMODE = L : 256 fs)
; MASTER CLOCK SELECT
(L : CLK = 256 fs, 12.288 MHz @fs = 48 kHz)
(H : CLK = 384 fs, 18.432 MHz @fs = 48 kHz)
; POWER DOWN FOR DIGITAL SECTION
; 18/16 BIT SELECT (L : 16-BIT, H : 18-BIT)
; INTERFACE CLOCK SELECT
(L : SUB MODE)
(H : MASTER MODE)
; TEST
; REFERENCE VOLTAGE
;
;
;
;
;
PD
SEL 18
SMODE
TST 2, 4
V REF IN
OUTPUT
SDATA
V REF
; SERIAL DATA
; REFERENCE VOLTAGE (
_2.5V
)
INPUT/OUTPUT
; FRAME SYNC CLOCK
FSYNC
(SUB MODE : FSYNC INPUT)
(MASTER MODE : FSYNC OUTPUT)
; INPUT CHANNEL SELECT
L/
R
(SUB MODE : fs CLK INPUT)
(MASTER MODE : fs CLK OUTPUT)
; SERIAL DATA CLOCK
SCLK
(SUB MODE : SCLK INPUT)
(MASTER MODE : SCLK OUTPUT)
TST 1, 3
; TEST
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