Features
•
High Performance, Low Power AVR
®
8-bit Microcontroller
•
Advanced RISC Architecture
– 131 Powerful Instructions - Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 4 MIPS Throughput at 4 MHz
High Endurance Non-volatile Memorie segments
– 8K/16K Bytes of In-System Self-Programmable Flash Program
Memory(ATmega8HVA/16HVA)
– 256 Bytes EEPROM
– 512 Bytes Internal SRAM
– Write/Erase cycles: 10,000 Flash/100,000 EEPROM
– Data Retention: 20 years at 85°C /100 years at 25°C
(1)
– Programming Lock for Software Security
Battery Management Features
– One or Two Cells in Series
– Over-current Protection (Charge and Discharge)
– Short-circuit Protection (Discharge)
– High Voltage Outputs to Drive N-Channel Charge/Discharge FETs
Peripheral Features
– Two configurable 8- or 16-bit Timers with Separate Prescaler, Optional Input
Capture (IC), Compare Mode and CTC
– SPI - Serial Programmable Interface
– 12-bit Voltage ADC, Four External and One Internal ADC Inputs
– High Resolution Coulomb Counter ADC for Current Measurements
– Programmable Watchdog Timer
Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-System Programmable via SPI ports
– Power-on Reset
– On-chip Voltage Regulator with Short-circuit Monitoring Interface
– External and Internal Interrupt Sources
– Sleep Modes:
Idle, ADC Noise Reduction, Power-save, and Power-off
Additional Secure Authentication Features available only under NDA
Packages
– 36-pad LGA
– 28-lead TSOP
Operating Voltage: 1.8 - 9V
Maximum Withstand Voltage (High-voltage pins): 28V
Temperature Range: - 20°C to 85°C
Speed Grade: 1-4 MHz
•
•
8-bit
Microcontroller
with 8K/16K
Bytes In-System
Programmable
Flash
ATmega8HVA
ATmega16HVA
Preliminary
Summary
•
•
•
•
•
•
•
•
8024AS–AVR–04/08
1. Pin Configurations
1.1
LGA
Figure 1-1.
LGA - Pinout ATmega8HVA/16HVA
1
A
B
C
D
E
2
3
4
5
6
7
8
Figure 1-2.
1
A
B
C
D
E
DNC
CF2P
VREF
PI
DNC
LGA - pinout ATmega8HVA/16HVA
2
PV2
CF2N
VREFGND
NI
DNC
3
PV1
VFET
VREG
GND
PA1
4
NV
CF1P
CF1N
GND
PA0
5
GND
GND
VCC
GND
PB1
6
OC
PC0
GND
PB2
PB0
7
OD
DNC
GND
PB3
RESET
8
DNC
GND
BATT
GND
DNC
2
ATmega8HVA/16HVA
8024AS–AVR–04/08
ATmega8HVA/16HVA
1.2
TSOP
Figure 1-3.
TSOP - pinout ATmega8HVA/16HVA
PV2
PV1
NV
GND
VFET
CF1P
CF1N
CF2P
CF2N
VREG
VREF
VREFGND
PI
NI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OD
OC
GND
BATT
PC0 (RXD/TXD/INT0)
VCC
GND
PB3 (MISO/INT2)
PB2 (MOSI/INT1)
PB1 (SCK)
PB0 (SS/CKOUT)
PA2 (RESET/dW)
PA1 (ADC1/SGND/T1)
PA0 (ADC0/SGND/T0)
1.3
1.3.1
Pin Descriptions
VFET
Input to the internal voltage regulator.
1.3.2
VCC
Digital supply voltage. Normally connected to VREG.
1.3.3
VREG
Output from the internal voltage regulator.
1.3.4
CF1P/CF1N/CF2P/CF2N
CF1P/CF1N/CF2P/CF2N are the connection pins for connecting external fly capacitors to the
step-up regulator.
1.3.5
VREF
Internal Voltage Reference for external decoupling.
1.3.6
VREFGND
Ground for decoupling of Internal Voltage Reference. Do not connect to GND or SGND on PCB.
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8024AS–AVR–04/08
1.3.7
GND
Ground
1.3.8
Port A (PA1..PA0)
Port A serves as a low-voltage 2-bit bi-directional I/O port with internal pull-up resistors (selected
for each bit). As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port A also serves the functions of various special features of the ATmega8HVA/16HVA as
listed in
”Alternate Functions of Port A” on page 70.
1.3.9
Port B (PB3..PB0)
Port B is a low-voltage 4-bit bi-directional I/O port with internal pull-up resistors (selected for
each bit). As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATmega8HVA/16HVA as
listed in
”Alternate Functions of Port B” on page 71.
1.3.10
PC0
Port C serves the functions of various special features of the ATmega8HVA/16HVA as listed in
”Alternate Functions of Port C” on page 61.
1.3.11
OC
High voltage output to drive Charge FET.
1.3.12
OD
High voltage output to drive Discharge FET.
1.3.13
NI
NI is the filtered negative input from the current sense resistor.
1.3.14
PI
PI is the filtered positive input from the current sense resistor.
1.3.15
NV/PV1/PV2
NV, PV1, and PV2 are the inputs for battery cells 1 and 2.
1.3.16
BATT
Input for detecting when a charger is connected.
1.3.17
RESET/dw
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 11 on page
38. Shorter pulses are not guaranteed to generate a reset. This pin is also used as debugWIRE
communication pin.
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ATmega8HVA/16HVA
8024AS–AVR–04/08
ATmega8HVA/16HVA
2. Overview
The ATmega8HVA/16HVA is a monitoring and protection circuit for 1-cell and 2-cell Li-ion appli-
cations with focus on high security/authentication, accurate monitoring, low cost and high
utilization of the cell energy. The device contains secure authentication features as well as
autonomous battery protection during charging and discharging. The chip allows very accurate
accumulated current measurements using an 18-bit ADC with a resolution of 0.84 µV. The fea-
ture set makes the ATmega8HVA/16HVA a key component in any system focusing on high
security, battery protection, accurate monitoring, high system utilization and low cost.
Figure 2-1.
Block Diagram
PB3..0
PC0
PB0
Oscillator
Circuits /
Clock
Generation
Oscillator
Sampling
Interface
Program
Logic
Flash
RESET/dW
Power
Supervision
POR &
RESET
debugWIRE
PORTB (4)
PORTC (1)
FET
Control
OC
OD
Watchdog
Oscillator
VCC
Watchdog
Timer
SPI
8/16-bit T/C0
Battery
Protection
PV2
PV1
NV
SRAM
8/16-bit T/C1
Voltage
ADC
VPTAT
CPU
EEPROM
Voltage
Reference
VREF
VREFGND
PI
NI
GND
BATT
Charger
Detect
Security
Module
DATA BUS
Coulumb
Counter ADC
VFET
VREG
Voltage
Regulator
Voltage Regulator
Monitor Interface
PORTA (2)
PA1..0
CF1N
CF1P
CF2P
CF2N
PA1..0
A combined step-up and linear voltage regulator ensures that the chip can operate with supply
voltages as low as 1.8V for 1-cell applications. The regulator automatically switches to linear
mode when the input voltage is sufficiently high, thereby ensuring a minimum power consump-
tion at all times. For 2-cell applications, only linear regulation is enabled. The regulator
capabilities, combined with an extremely low power consumption in the power saving modes,
greatly enhances the cell energy utilization compared to existing solutions.
The chip utilizes Atmel's patented Deep Under-voltage Recovery (DUVR) mode that supports
pre-charging of deeply discharged battery cells without using a separate Pre-charge FET.
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8024AS–AVR–04/08