74HC374
Octal 3−State Non−Inverting
D Flip−Flop
High−Performance Silicon−Gate CMOS
The 74HC374 is identical in pinout to the LS374. The device inputs
are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
Data meeting the setup time is clocked to the outputs with the rising
edge of the clock. The Output Enable input does not affect the states of
the flip−flops, but when Output Enable is high, the outputs are forced
to the high−impedance state; thus, data may be stored even when the
outputs are not enabled.
The HC374 is identical in function to the HC574A which has the
input pins on the opposite side of the package from the output. This
device is similar in function to the HC534A which has inverting
outputs.
Features
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MARKING
DIAGRAM
20
20
1
TSSOP−20
DT SUFFIX
CASE 948E
1
HC
374
ALYW
G
G
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
•
ESD Performance: HBM
>
2000 V; Machine Model
>
200 V
•
Chip Complexity: 266 FETs or 66.5 Equivalent Gates
•
This is a Pb−Free Device
HC374 = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
©
Semiconductor Components Industries, LLC, 2007
March, 2007
−
Rev. 0
1
Publication Order Number:
74HC374/D
74HC374
PIN ASSIGNMENT
LOGIC DIAGRAM
D0
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
CLOCK
3
4
7
8
13
14
17
18
11
2
5
6
9
12
15
16
19
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
NONINVERTING
OUTPUTS
OUTPUT
ENABLE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CLOCK
FUNCTION TABLE
1
PIN 20 = V
CC
PIN 10 = GND
Inputs
Output
Enable
L
L
L
H
Clock
D
H
L
X
X
Output
Q
H
L
No Change
Z
OUTPUT ENABLE
L,H,
X
X = don’t care
Z = high impedance
ORDERING INFORMATION
Device
74HC374DTR2G
Package
TSSOP−20*
Shipping
†
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
74HC374
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS
Symbol
V
CC
V
in
I
in
I
out
I
CC
P
D
T
stg
T
L
V
out
Parameter
Value
Unit
V
V
V
mA
mA
mA
mW
_C
_C
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
– 0.5 to + 7.0
– 0.5 to V
CC
+ 0.5
– 0.5 to V
CC
+ 0.5
±20
±35
±75
450
– 65 to + 150
260
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air,
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(TSSOP Package)
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — TSSOP Package:
−
6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
, V
out
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time
(Figure 1)
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Min
2.0
0
– 55
0
0
0
Max
6.0
V
CC
+ 125
1000
500
400
Unit
V
V
_C
ns
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3
74HC374
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
Symbol
V
IH
Parameter
Minimum High−Level Input Voltage
Test Conditions
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
|
v
20
mA
V
CC
(V)
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
v
2.4 mA
|I
out
|
v
6.0 mA
|I
out
|
v
7.8 mA
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
v
2.4 mA
|I
out
|
v
6.0 mA
|I
out
|
v
7.8 mA
3.0
4.5
6.0
6.0
6.0
– 55 to
25_C
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
1.90
4.40
5.90
2.48
2.98
5.48
0.10
0.10
0.10
0.26
0.26
0.26
±0.1
±0.5
v
85_C
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
1.90
4.40
5.90
2.34
3.84
5.34
0.10
0.10
0.10
0.33
0.33
0.33
±1.0
±5.0
v
125_C
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
1.90
4.40
5.90
2.20
3.70
5.20
0.10
0.10
0.10
0.40
0.40
0.40
±1.0
±10
Unit
V
V
IL
Maximum Low−Level Input Voltage
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
|
v
20
mA
V
V
OH
Minimum High−Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
|
v
20
mA
V
in
= V
IH
or V
IL
V
V
V
V
OL
Maximum Low−Level Output
Voltage
V
in
= V
IH
or V
IL
|I
out
|
v
20
mA
V
in
= V
IH
or V
IL
V
mA
mA
I
in
I
OZ
Maximum Input Leakage Current
Maximum Three−State
Leakage Current
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
Output in High−Impedance State
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
V
in
= V
CC
or GND
I
out
= 0
mA
I
CC
6.0
4.0
40
40
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book
(DL129/D).
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4
74HC374
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
Guaranteed Limit
Symbol
f
max
Parameter
Maximum Clock Frequency (50% Duty Cycle)
V
CC
(V)
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
– 55 to
25_C
6
15
30
35
125
80
25
21
150
100
30
26
150
100
30
26
75
27
15
13
10
15
v
85_C
5
10
24
28
155
110
31
26
190
125
38
33
190
125
38
33
95
32
19
16
10
15
v
125_C
4
8
20
24
190
130
38
32
225
150
45
38
225
150
45
38
110
36
22
19
10
15
Unit
MHz
t
PLH
t
PHL
Maximum Propagation Delay, Input Clock to Q
(Figures 1 and 5)
ns
t
PLZ
t
PHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
ns
t
PLZ
t
PHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
ns
t
TLH
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
ns
C
in
C
out
Maximum Input Capacitance
Maximum Three−State Output Capacitance
(Output in High−Impedance State)
pF
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (Per Enabled Output)*
34
pF
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC2
f + I
CC
V
CC
. For load considerations, see Chapter 2 of the
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
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