MC14027B
Dual J-K Flip-Flop
The MC14027B dual J−K flip−flop has independent J, K, Clock (C),
Set (S) and Reset (R) inputs for each flip−flop. These devices may be
used in control, register, or toggle functions.
Features
•
•
•
•
•
•
•
•
•
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic Swing Independent of Fanout
Logic Edge−Clocked Flip−Flop Design
Logic State is Retained Indefinitely with Clock Level Either High or
Low; Information is Transferred to the Output Only on the
Positive−Going Edge of the Clock Pulse
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
Pin−for−Pin Replacement for CD4027B
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
This Device is Pb−Free and is RoHS Compliant
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SOIC−16
D SUFFIX
CASE 751B
PIN ASSIGNMENT
Q
A
Q
A
C
A
R
A
K
A
J
A
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
Q
B
Q
B
C
B
R
B
K
B
J
B
S
B
MAXIMUM RATINGS
(Voltages Referenced to V
SS
)
Symbol
V
DD
V
in
, V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation, per Package
(Note 1)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8−Second Soldering)
Value
−0.5 to +18.0
−0.5 to V
DD
+ 0.5
±
10
500
−55 to +125
−65 to +150
260
Unit
V
V
S
A
V
SS
MARKING DIAGRAM
mA
16
mW
°C
°C
°C
A
WL
YY, Y
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
14027BG
AWLYWW
1
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
≤
(V
in
or V
out
)
≤
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 8
Publication Order Number:
MC14027B/D
MC14027B
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
−55_C
Characteristic
Output Voltage
V
in
= V
DD
or 0
V
in
= 0 or V
DD
“0” Level
Symbol
V
OL
V
DD
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
“1” Level
V
IH
5.0
10
15
5.0
5.0
10
15
I
OL
5.0
10
15
15
−
5.0
10
15
5.0
10
15
Min
−
−
−
4.95
9.95
14.95
−
−
−
3.5
7.0
11
–3.0
–0.64
–1.6
–4.2
0.64
1.6
4.2
−
−
−
−
−
Max
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
−
−
−
−
−
−
−
−
−
−
±0.1
−
1.0
2.0
4.0
Min
−
−
−
4.95
9.95
14.95
−
−
−
3.5
7.0
11
–2.4
–0.51
−1.3
−3.4
0.51
1.3
3.4
−
−
−
−
−
25_C
Typ
(Note 2)
0
0
0
5.0
10
15
2.25
4.50
6.75
2.75
5.50
8.25
–4.2
–0.88
–2.25
−8.8
0.88
2.25
8.8
±
0.00001
5.0
0.002
0.004
0.006
Max
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
−
−
−
−
−
−
−
−
−
−
±0.1
7.5
1.0
2.0
4.0
125_C
Min
−
−
−
4.95
9.95
14.95
−
−
−
3.5
7.0
11
–1.7
−0.36
–0.9
−2.4
0.36
0.9
2.4
−
−
−
−
−
Max
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
−
−
−
−
−
−
−
−
−
−
±1.0
−
30
60
120
mAdc
Vdc
Unit
Vdc
“1” Level
V
OH
Vdc
Input Voltage
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
(V
O
= 0.5 or 4.5 Vdc)
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
Output Drive Current
(V
OH
= 2.5 Vdc)
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
(V
OL
= 0.4 Vdc)
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
Input Current
Input Capacitance
(V
in
= 0)
Quiescent Current
(Per Package)
“0” Level
V
IL
Vdc
I
OH
Source
mAdc
Sink
I
in
C
in
I
DD
mAdc
pF
mAdc
Total Supply Current (Notes 3 & 4)
(Dynamic plus Quiescent,
Per Package)
(C
L
= 50 pF on all outputs, all
buffers switching)
I
T
I
T
= (0.8
mA/kHz)
f + I
DD
I
T
= (1.6
mA/kHz)
f + I
DD
I
T
= (2.4
mA/kHz)
f + I
DD
mAdc
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
I
T
(C
L
) = I
T
(50 pF) + (C
L
− 50) Vfk
where: I
T
is in
mA
(per package), C
L
in pF, V = (V
DD
− V
SS
) in volts, f in kHz is input frequency, and k = 0.002.
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3
MC14027B
SWITCHING CHARACTERISTICS
(Note 5) (C
L
= 50 pF, T
A
= 25_C)
Characteristic
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) C
L
+ 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) C
L
+ 12.5 ns
Propagation Delay Times**
Clock to Q, Q
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 90 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 42 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 25 ns
Set to Q, Q
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 90 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 42 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 25 ns
Reset to Q, Q
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 265 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 67 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 50 ns
Setup Times
t
su
Symbol
t
TLH
,
t
THL
V
DD
5.0
10
15
Min
−
−
−
Typ
(Note 6)
Max
200
100
80
ns
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5
10
15
5
10
15
t
WH
5.0
10
15
−
−
−
−
−
−
−
−
−
140
50
35
140
50
35
330
110
75
−
−
−
−
−
−
90
45
35
50
25
20
250
100
70
175
75
50
175
75
50
350
100
75
70
25
17
70
25
17
165
55
38
3.0
9.0
13
−
−
−
10
5
3
– 30
– 15
– 10
125
50
35
350
150
100
350
150
100
450
200
150
−
−
−
−
−
−
−
−
−
1.5
4.5
6.5
15
5.0
4.0
−
−
−
−
−
−
−
−
−
ns
ns
Unit
ns
100
50
40
t
PLH
,
t
PHL
Hold Times
t
h
ns
Clock Pulse Width
t
WH
, t
WL
ns
Clock Pulse Frequency
f
cl
MHz
Clock Pulse Rise and Fall Time
t
TLH
, t
THL
ms
Removal Times
Set
t
rem
ns
Reset
Set and Reset Pulse Width
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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4
MC14027B
20 ns
J
90%
50%
10%
20 ns
K
t
su
20 ns
V
DD
V
SS
V
DD
V
SS
20 ns
V
DD
V
SS
20 ns
90%
SET OR
RESET
t
w
CLOCK
t
THL
V
OL
t
PLH
t
PHL
Q or Q
50%
V
OL
20 ns
V
DD
50%
10%
t
rem
20 ns
90%
50%
t
w
20 ns
10%
V
SS
V
DD
V
SS
V
OH
20 ns
90%
50%
10%
t
su
20 ns
C
t
WH
t
PLH
Q
t
TLH
1
f
cl
90%
50%
10%
90%
50%
10%
t
WL
t
h
t
PHL
V
OH
Inputs R and S low.
For the measurement of t
WH
, I/f
cl
, and P
D
the Inputs J and K are kept high.
Figure 1. Dynamic Signal Waveforms
(J, K, Clock, and Output)
Figure 2. Dynamic Signal Waveforms
(Set, Reset, Clock, and Output)
LOGIC DIAGRAM
(1/2 of Device Shown)
S
Q
C
J
C
C
C
K
C
C
C
R
C
Q
C
C
C
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