PTN3393
2-lane DisplayPort to VGA adapter IC
Rev. 4 — 10 June 2014
Product data sheet
1. General description
The PTN3393 is a DisplayPort to VGA adapter IC designed to connect a DisplayPort
source to a VGA sink. The PTN3393 integrates a DisplayPort receiver and a high-speed
triple video digital-to-analog converter that supports display resolutions from VGA to
WUXGA (see
Table 5).
The PTN3393 supports either one or two DisplayPort v1.1a lanes
operating at either 2.7 Gbit/s or 1.62 Gbit/s per lane. The PTN3393 has ‘Flash-over-AUX’
capability enabling simple firmware upgradability in the field.
The PTN3393 supports I
2
C-bus over AUX per
DisplayPort v1.1a specification
(Ref.
1),
and bridges the VESA DDC channel to the DisplayPort Interface.
The PTN3393 is designed for single supply and minimizes application costs. It can be
powered directly from the DisplayPort source side 3.3 V supply without a need for
additional core voltage regulator. The VGA output is powered down when there is no valid
DisplayPort source data being transmitted. The PTN3393 also aids in monitor detection
by performing load sensing and reporting sink connection status to the source.
2. Features and benefits
2.1 VESA-compliant DisplayPort v1.1a converter
Main Link: 1-lane and 2-lane modes supported
HBR (High Bit Rate) at 2.7 Gbit/s per lane
RBR (Reduced Bit Rate) at 1.62 Gbit/s per lane
BER (Bit Error Rate) better than 10
9
Down-spreading SSC (Spread Spectrum Clocking) supported
1 MHz AUX channel
Supports native AUX CH syntax
Supports I
2
C-bus over AUX CH syntax
Hot Plug Detect (HPD) signal to the source
Cost-effective design optimized for VGA application
2.2 DDC channel output
Supports 100 kbit/s I
2
C-bus speed, declared in DPCD register
Support of I
2
C-bus speed control by DisplayPort source via DPCD registers,
facilitating use of longer VGA cables
I
2
C Over Aux feature facilitates full support of MCCS, DDC-CI, and DDC protocols
(see
Ref. 2)
NXP Semiconductors
PTN3393
2-lane DisplayPort to VGA adapter IC
2.3 Analog video output
VSIS 1.2 compliance (Ref.
3)
for all supported video output modes
Analog RGB current-source outputs
VSYNC and HSYNC outputs
Pixel clock up to 240 MHz
Triple 8-bit Digital-to-Analog Converter (DAC)
Direct drive of double terminated 75
load with standard 700 mV (peak-to-peak)
signals
2.4 General features
Supports ‘Flash-over-AUX’ field upgradability
Monitor presence detection. Connection/disconnection reported via HPD IRQ and
DPCD update.
All display resolutions from VGA to WUXGA are supported
1
, including e.g.:
WUXGA: 6 bits, 1920
1200, 60 Hz, 193 MHz pixel clock rate
WUXGA: 1920
1200, 60 Hz, reduced blanking, 154 MHz pixel clock rate
UXGA: 1600
1200, 60 Hz, 162 MHz pixel clock rate
SXGA: 1280
1024, 60 Hz, 108 MHz pixel clock rate
XGA: 1024
768, 60 Hz, 65 MHz pixel clock rate
SVGA: 800
600, 60 Hz, 40 MHz pixel clock rate
VGA: 640
480, 60 Hz, 25 MHz pixel clock rate
Any resolution and refresh rates are supported up to 8 bit color
Bits per color (bpc) supported
1
6, 8 bits supported
10, 12, 16 bits supported by truncation to 8 MSBs
All VGA colorimetry formats (RGB) supported
Power modes
Active-mode power consumption:
~600 mW at UXGA / 162 MHz pixel clock
~500 mW at SXGA / 108 MHz pixel clock
~40 mW at Low-power mode or before link training started
On-board crystal oscillator for use with external 27 MHz crystal
ESD protection: 7 kV ESD HBM JEDEC
3.3 V
10 % power supply
Commercial temperature range: 0
C
to 85
C
40-pin HVQFN, 6 mm
6 mm
0.85 mm (nominal); 0.5 mm pitch; lead-free package
1.
Except for color depth beyond 8 bits, display resolutions and refresh rates are only limited to those which a standard 2-lane
DisplayPort configuration is able to support.
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
PTN3393
Product data sheet
Rev. 4 — 10 June 2014
2 of 30
NXP Semiconductors
PTN3393
2-lane DisplayPort to VGA adapter IC
3. Applications
Dongle PC accessory
Dongle connected to PC DisplayPort output and connected to RGB monitor via
VGA cable
PTN3393 is powered by the DP_PWR pin on the DisplayPort connector
Desktop and notebook computers
Notebook docking stations
4. Ordering information
Table 1.
Ordering information
Topside mark
PTN3393
PTN3393
Package
Name
PTN3393BS
[1]
PTN3393BS/FX
[2]
HVQFN40
HVQFN40
Description
plastic thermal enhanced very thin quad flat package;
no leads; 40 terminals; 6
6
0.85 mm
plastic thermal enhanced very thin quad flat package;
no leads; 40 terminals; 6
6
0.85 mm
Version
SOT618-6
SOT618-6
Type number
[1]
[2]
PTN3393BS uses latest firmware version.
PTN3393BS/FX uses specific firmware version (‘X’ = 1, 2, 3, etc., and changes according to firmware version).
4.1 Ordering options
Table 2.
Ordering options
Orderable
part number
PTN3393BSY
PTN3393BS/FXY
Package
Packing method
Minimum
order
quantity
4000
4000
Temperature
Type number
PTN3393BS
[1]
PTN3393BS/FX
[2]
HVQFN40 Reel 13” Q1/T1
*Standard mark SMD dry pack
HVQFN40 Reel 13” Q1/T1
*Standard mark SMD dry pack
T
amb
= 0
C
to +85
C
T
amb
= 0
C
to +85
C
[1]
[2]
PTN3393BS uses latest firmware version.
PTN3393BS/FX uses specific firmware version (‘X’ = 1, 2, 3, etc., and changes according to firmware version).
PTN3393
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 10 June 2014
3 of 30
NXP Semiconductors
PTN3393
2-lane DisplayPort to VGA adapter IC
5. Functional diagram
PTN3393
RX PHY
ANALOG
SUBSYSTEM
DIFF CDR,
RCV S2P
RX PHY DIGITAL
DE-SCRAM
ISOCHRONOUS LINK
VIDEO DAC SUBSYSTEM
MONITOR
PRESENCE
DETECT
R[7:0]
DAC
DAC
DAC
R
VGA
OUTPUT
G
B
HSYNC
VSYNC
INTERFACE DE-SKEWING
10b/8b
lane 0
TIME
CONV.
G[7:0]
MAIN
STREAM
B[7:0]
H, V
sync
TIMING RECOVERY
V
bias
DIFF CDR,
RCV S2P
DE-SCRAM
10b/8b
lane 1
DPCD
REGISTERS
CONTROL
FLASH
MCU
V
bias
RCV
AUX
DRV
RX ACLI
V
bias
RX DIGITAL SUBSYSTEM
002aah229
MANCHESTER
CODEC
AUX COMMAND
LEVEL MODULE
I
2
C-BUS
MASTER
SCL
SDA
Fig 1.
Functional diagram
PTN3393
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 10 June 2014
4 of 30
NXP Semiconductors
PTN3393
2-lane DisplayPort to VGA adapter IC
6. Pinning information
6.1 Pinning
36 VDDD33_CORE
35 LDOCAP_DIG
34 OSC_OUT
33 OSC_IN
40 S3
39 S2
38 S1
VDDA33_AUX
LDOCPA_AUX
AUX_P
AUX_N
RRX
ML0_P
ML0_N
n.c.
ML1_P
1
2
3
4
5
6
7
8
9
GND
(1)
RESET 11
CLK_O 12
HPD 13
VDDA33_DP 14
TCK 15
TDO 16
TMS 17
TRST 18
TDI 19
SCL 20
37 S0
terminal 1
index area
31 RED
30 RSET
29 n.c.
28 GRN
27 VDDA33_DAC
26 BLU
25 HSYNC
24 VSYNC
23 n.c.
22 SDA
21 VDDD33_IO
002aah226
PTN3393BS
ML1_N 10
Transparent top view
Fig 2.
Pin configuration for HVQFN40
PTN3393
All information provided in this document is subject to legal disclaimers.
32 n.c.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 4 — 10 June 2014
5 of 30
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