24AA024/24LC024/24AA025/24LC025
2K I
2
C
™
Serial EEPROM
Device Selection Table
Part
V
CC
Range
Number
Max
Clock
Temp. Write
Range Protect
I
I
I
I
Yes
No
Yes
No
Description
The Microchip Technology Inc. 24AA024/24LC024/
24AA025/24LC025 is a 2 Kbit Serial Electrically
Erasable PROM with a voltage range of 1.8V to 5.5V.
The device is organized as a single block of 256 x 8-bit
memory with a 2-wire serial interface. Low current
design permits operation with typical standby and
active currents of only 1
µA
and 1 mA, respectively.
The device has a page write capability for up to 16
bytes of data. Functional address lines allow the
connection of up to eight 24AA024/24LC024/
24AA025/24LC025 devices on the same bus for up to
16K bits of contiguous EEPROM memory. The device
is available in the standard 8-pin PDIP, 8-pin SOIC
(150 mil), TSSOP and MSOP packages.
24AA024 1.8V - 5.5V 400 KHz
(1)
24AA025 1.8V - 5.5V 400 KHz
(1)
24LC024 2.5V - 5.5V
24LC025 2.5V - 5.5V
Note 1:
400 KHz
400 KHz
100 KHz for V
CC
< 2.5V
Features
• Single supply with operation from 1.8V to 5.5V
• Low-power CMOS technology
- 1 mA active current typical
- 1
µA
standby current typical at 5.5V
• Organized as a single block of 256 bytes (256 x 8)
• Hardware write protection for entire array
(24XX024)
• 2-wire serial interface bus, I
2
C™ compatible
• 100 kHz and 400 kHz clock compatibility
• Page write buffer for up to 16 bytes
• Self-timed write cycle (including auto-erase)
• 10 ms max. write cycle time
• Address lines allow up to eight devices on bus
• 1,000,000 erase/write cycles
• ESD protection > 4,000V
• Data retention > 200 years
• 8-pin PDIP, SOIC, TSSOP and MSOP packages
• Available for extended temperature ranges
- Industrial (I): -40°C to +85°C
Package Types
PDIP/SOIC
A0
A1
A2
V
SS
TSSOP/MSOP
A0
A1
A2
V
SS
1
2
3
4
8
7
6
5
1
8
V
CC
WP*
SCL
SDA
24XX024
24XX025
24XX024
24XX025
2
3
4
7
6
5
V
CC
WP*
SCL
SDA
Block Diagram
A0 A1 A2
WP*
HV Generator
Pin Function Table
Name
V
SS
SDA
SCL
V
CC
A0, A1, A2
WP
Ground
Serial Data
Serial Clock
1.8V to 5.5V Power Supply
Chip Selects
Hardware Write-Protect (24LC024)
Function
I/O
Control
Logic
Memory
Control
Logic
XDEC
EEPROM
Array
SDA SCL
V
CC
V
SS
Write-Protect
Circuitry
YDEC
Sense Amp.
R/W Control
Note:
*WP pin available only on 24XX024. This pin
has no internal connection on 24XX025.
2004 Microchip Technology Inc.
DS21210G-page 1
24AA024/24LC024/24AA025/24LC025
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
SS
......................................................................................................... -0.6V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins
......................................................................................................................................................≥
4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
V
CC
= 1.8V to 5.5V
Industrial (I): T
A
= -40°C to +85°C
Symbol
V
IH
V
IL
V
HYS
V
OL
I
LI
I
LO
C
IN
, C
OUT
I
CC
Read
I
CC
Write
I
CCS
Min.
0.7 V
CC
—
0.05 V
CC
—
—
—
—
—
—
—
Max.
—
0.3 V
CC
—
0.40
±1
±1
10
1
3
1
Units
V
V
V
V
µA
µA
pF
mA
mA
µA
—
—
(Note)
I
OL
= 3.0 mA, V
CC
= 4.5V
I
OL
= 2.1 mA, V
CC
= 2.5V
V
IN
= 0.1V to 5.5V, WP = V
SS
V
OUT
= 0.1V to 5.5V
V
CC
= 5.0V
(Note)
T
A
= 25°C, f = 1 MHz
V
CC
= 5.5V, SCL = 400 kHz
V
CC
= 5.5V
V
CC
= 5.5V, SDA = SCL = V
CC
WP = V
SS
, A0, A1, A2 = V
SS
Conditions
All parameters apply across the
specified operating ranges unless
otherwise noted.
Parameter
SCL and SDA pins:
High-level input voltage
Low-level input voltage
Hysteresis of Schmitt Trigger inputs
Low-level output voltage
Input leakage current
Output leakage current
Pin capacitance (all inputs/outputs)
Operating current
Standby current
Note:
This parameter is periodically sampled and not 100% tested.
DS21210G-page 2
2004 Microchip Technology Inc.
24AA024/24LC024/24AA025/24LC025
TABLE 1-2:
AC CHARACTERISTICS
V
CC
= 1.8V to 5.5V
Industrial (I):
T
A
= -40°C to +85°C
Vcc = 2.5V - 5.5V
FAST MODE
Min.
—
600
1300
—
—
600
600
0
100
600
—
1300
Max.
400
—
—
300
300
—
—
—
—
—
900
—
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
—
(Note 1)
(Note 1)
After this period the first
clock pulse is generated
Only relevant for repeated
Start condition
(Note 2)
—
—
(Note 2)
Time the bus must be free
before a new transmission
can start
(Note 1),
C
B
≤
100 pF
All parameters apply across the specified
operating ranges unless otherwise noted.
STD MODE
Parameter
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
Start condition hold time
Start condition setup time
Data input hold time
Data input setup time
Stop condition setup time
Output valid from clock
Bus free time
Symbol
Min.
F
CLK
T
HIGH
T
LOW
T
R
T
F
T
HD
:
STA
T
SU
:
STA
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
T
AA
T
BUF
—
4000
4700
—
—
4000
4700
0
250
4000
—
4700
Max.
100
—
—
1000
300
—
—
—
—
—
3500
—
Units
Remarks
T
OF
Output fall time from V
IH
—
250
20 +0.1
250
ns
minimum to V
IL
maximum
C
B
—
50
—
50
ns
(Note 3)
Input filter spike suppression T
SP
(SDA and SCL pins)
—
10
—
10
ms Byte or Page mode
Write-cycle time
T
WC
Endurance
1M
—
1M
—
cycles 25°C,
(Note 4)
Note 1:
Not 100% tested. C
B
= total capacitance of one bus line in pF.
2:
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3:
The combined T
SP
and V
HYS
specifications are due to Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4:
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be downloaded at
www.microchip.com.
FIGURE 1-1:
BUS TIMING DATA
T
F
T
HIGH
T
R
SCL
T
SU
:
STA
T
LOW
T
HD
:
DAT
T
SU
:
DAT
T
SU
:
STO
SDA
IN
T
SP
T
HD
:
STA
T
BUF
T
AA
SDA
OUT
2004 Microchip Technology Inc.
DS21210G-page 3
24AA024/24LC024/24AA025/24LC025
2.0
2.1
PIN DESCRIPTIONS
SDA Serial Data
3.0
FUNCTIONAL DESCRIPTION
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open-drain
terminal, therefore the SDA bus requires a pull-up
resistor to V
CC
(typical 10 kΩ for 100 kHz, 2 kΩ for
400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.2
SCL Serial Clock
The 24AA024/24LC024/24AA025/24LC025 supports
a bidirectional, 2-wire bus and data transmission
protocol. A device that sends data onto the bus is
defined as transmitter, while a device receiving data
is defined as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access and generates the
Start and Stop conditions, while the 24AA024/
24LC024/24AA025/24LC025 works as slave. Both
master and slave can operate as transmitter or
receiver, but the master device determines which
mode is activated.
The SCL input is used to synchronize the data transfer
from and to the device.
2.3
A0, A1, A2
The levels on the A0, A1 and A2 inputs are compared
with the corresponding bits in the slave address. The
chip is selected if the compare is true.
Up to eight 24AA024/24LC024/24AA025/24LC025
devices may be connected to the same bus by using
different Chip Select bit combinations. These inputs
must be connected to either V
CC
or V
SS
.
2.4
WP (24XX024 Only)
WP is the hardware write-protect pin. It must be tied to
V
CC
or V
SS
. If tied to Vcc, hardware write protection is
enabled. If WP is tied to Vss, the hardware write
protection is disabled. Note that the WP pin is available
only on the 24XX024. This pin is not internally
connected on the 24LC025.
2.5
Noise Protection
The 24AA024/24LC024/24AA025/24LC025 employs a
V
CC
threshold detector circuit which disables the inter-
nal erase/write logic if the V
CC
is below 1.5 volts at
nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
DS21210G-page 4
2004 Microchip Technology Inc.
24AA024/24LC024/24AA025/24LC025
4.0
BUS CHARACTERISTICS
The following
bus protocol
has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is,
theoretically, unlimited, (though only the last sixteen will
be stored when performing a write operation). When an
overwrite does occur, it will replace data in a first-in
first-out fashion.
4.1
Bus Not Busy (A)
4.5
Acknowledge
Both data and clock lines remain high.
4.2
Start Data Transfer (B)
Each receiving device, when addressed, is required to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
Note:
The 24AA024/24LC024/24AA025/
24LC025 does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The device that acknowledges has to pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of
the acknowledge-related clock pulse. Of course, setup
and hold times must be taken into account. A master
must signal an end of data to the slave by not generating
an Acknowledge bit on the last byte that has been
clocked out of the slave. In this case, the slave must
leave the data line high to enable the master to generate
the Stop condition (Figure 4-2).
FIGURE 4-1:
SCL
SDA
(A)
(B)
DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS
(C)
(D)
(C)
(A)
Start
Condition
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
FIGURE 4-2:
ACKNOWLEDGE TIMING
Acknowledge
Bit
SCL
1
2
3
4
5
6
7
8
9
1
2
3
SDA
Data from transmitter
Transmitter must release the SDA line at this point allowing
the Receiver to pull the SDA line low to acknowledge the
previous eight bits of data.
Data from transmitter
Receiver must release the SDA line at this
point so the Transmitter can continue
sending data.
2004 Microchip Technology Inc.
DS21210G-page 5
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