Features
•
High Performance, Low Power 32-bit Atmel
®
AVR
®
Microcontroller
– Compact Single-Cycle RISC Instruction Set Including DSP Instruction Set
– Read-Modify-Write Instructions and Atomic Bit Manipulation
– Performing up to 1.51DMIPS/MHz
• Up to 126 DMIPS Running at 84MHz from Flash (1 Wait-State)
• Up to 63 DMIPS Running at 42MHz from Flash (0 Wait-State)
– Memory Protection Unit
Multi-Layer Bus System
– High-Performance Data Transfers on Separate Buses for Increased Performance
– 8 Peripheral DMA Channels (PDCA) Improves Speed for Peripheral
Communication
– 4 generic DMA Channels for High Bandwidth Data Paths
Internal High-Speed Flash
– 256KBytes, 128KBytes, 64KBytes versions
– Single-Cycle Flash Access up to 36MHz
– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed
– 4 ms Page Programming Time and 8ms Full-Chip Erase Time
– 100,000 Write Cycles, 15-year Data Retention Capability
– Flash Security Locks and User Defined Configuration Area
Internal High-Speed SRAM
– 64KBytes Single-Cycle Access at Full Speed, Connected to CPU Local Bus
– 64KBytes (2x32KBytes with independent access) on the Multi-Layer Bus System
Interrupt Controller
– Autovectored Low Latency Interrupt Service with Programmable Priority
System Functions
– Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator
– Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL),
– Watchdog Timer, Real-Time Clock Timer
External Memories
– Support SDRAM, SRAM, NandFlash (1-bit and 4-bit ECC), Compact Flash
– Up to 66 MHz
External Storage device support
– MultiMediaCard (MMC V4.3), Secure-Digital (SD V2.0), SDIO V1.1
– CE-ATA V1.1, FastSD, SmartMedia, Compact Flash
– Memory Stick: Standard Format V1.40, PRO Format V1.00, Micro
– IDE Interface
One Advanced Encryption System (AES) for AT32UC3A3256S, AT32UC3A3128S,
AT32UC3A364S, AT32UC3A4256S, AT32UC3A4128S and AT32UC3A364S
– 256-, 192-, 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications
– Buffer Encryption/Decryption Capabilities
Universal Serial Bus (USB)
– High-Speed USB 2.0 (480Mbit/s) Device and Embedded Host
– Flexible End-Point Configuration and Management with Dedicated DMA Channels
– On-Chip Transceivers Including Pull-Ups
One 8-channel 10-bit Analog-To-Digital Converter, multiplexed with Digital IOs.
Two Three-Channel 16-bit Timer/Counter (TC)
Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)
– Fractionnal Baudrate Generator
•
32-bit AVR
Microcontroller
AT32UC3A3256S
AT32UC3A3256
AT32UC3A3128S
AT32UC3A3128
AT32UC3A364S
AT32UC3A364
AT32UC3A4256S
AT32UC3A4256
AT32UC3A4128S
AT32UC3A4128
AT32UC3A464S
AT32UC3A464
•
•
•
•
•
•
•
•
•
•
•
32072H-AVR32–10/2012
AT32UC3A3
– Support for SPI and LIN
– Optionnal support for IrDA, ISO7816, Hardware Handshaking, RS485 interfaces and Modem Line
Two Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals
One Synchronous Serial Protocol Controller
– Supports I2S and Generic Frame-Based Protocols
Two Master/Slave Two-Wire Interface (TWI), 400kbit/s I2C-compatible
16-bit Stereo Audio Bitstream
– Sample Rate Up to 50 KHz
QTouch
®
Library Support
– Capacitive Touch Buttons, Sliders, and Wheels
– QTouch and QMatrix Acquisition
On-Chip Debug System (JTAG interface)
– Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace
110 General Purpose Input/Output (GPIOs)
– Standard or High Speed mode
– Toggle capability: up to 84MHz
Packages
– 144-ball TFBGA, 11x11 mm, pitch 0.8 mm
– 144-pin LQFP, 22x22 mm, pitch 0.5 mm
– 100-ball VFBGA, 7x7 mm, pitch 0.65 mm
Single 3.3V Power Supply
•
•
•
•
•
•
•
•
•
2
32072H–AVR32–10/2012
AT32UC3A3
1. Description
The AT32UC3A3/A4 is a complete System-On-Chip microcontroller based on the AVR32 UC
RISC processor running at frequencies up to 84MHz. AVR32 UC is a high-performance 32-bit
RISC microprocessor core, designed for cost-sensitive embedded applications, with particular
emphasis on low power consumption, high code density and high performance.
The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt con-
troller for supporting modern operating systems and real-time operating systems. Higher
computation capabilities are achievable using a rich set of DSP instructions.
The AT32UC3A3/A4 incorporates on-chip Flash and SRAM memories for secure and fast
access. 64 KBytes of SRAM are directly coupled to the AVR32 UC for performances optimiza-
tion. Two blocks of 32 Kbytes SRAM are independently attached to the High Speed Bus Matrix,
allowing real ping-pong management.
The Peripheral Direct Memory Access Controller (PDCA) enables data transfers between
peripherals and memories without processor involvement. The PDCA drastically reduces pro-
cessing overhead when transferring continuous and large data streams.
The Power Manager improves design flexibility and security: the on-chip Brown-Out Detector
monitors the power supply, the CPU runs from the on-chip RC oscillator or from one of external
oscillator sources, a Real-Time Clock and its associated timer keeps track of the time.
The device includes two sets of three identical 16-bit Timer/Counter (TC) channels. Each chan-
nel can be independently programmed to perform frequency measurement, event counting,
interval measurement, pulse generation, delay timing and pulse width modulation. 16-bit chan-
nels are combined to operate as 32-bit channels.
The AT32UC3A3/A4 also features many communication interfaces for communication intensive
applications like UART, SPI or TWI. The USART supports different communication modes, like
SPI Mode and LIN Mode. Additionally, a flexible Synchronous Serial Controller (SSC) is avail-
able. The SSC provides easy access to serial communication protocols and audio standards like
I2S.
The AT32UC3A3/A4 includes a powerfull External Bus Interface to interface all standard mem-
ory device like SRAM, SDRAM, NAND Flash or parallel interfaces like LCD Module.
The peripheral set includes a High Speed MCI for SDIO/SD/MMC and a hardware encryption
module based on AES algorithm.
The device embeds a 10-bit ADC and a Digital Audio bistream DAC.
The Direct Memory Access controller (DMACA) allows high bandwidth data flows between high
speed peripherals (USB, External Memories, MMC, SDIO, ...) and through high speed internal
features (AES, internal memories).
The High-Speed (480MBit/s) USB 2.0 Device and Host interface supports several USB Classes
at the same time thanks to the rich Endpoint configuration. The Embedded Host interface allows
device like a USB Flash disk or a USB printer to be directly connected to the processor. This
periphal has its own dedicated DMA and is perfect for Mass Storage application.
AT32UC3A3/A4 integrates a class 2+ Nexus 2.0 On-Chip Debug (OCD) System, with non-intru-
sive real-time trace, full-speed read/write memory access in addition to basic runtime control.
3
32072H–AVR32–10/2012
AT32UC3A3
2. Overview
2.1
Block Diagram
Figure 2-1.
TCK
TDO
TDI
TMS
Block Diagram
PBB
ID
VBOF
FLASH
CONTROLLER
USB_VBIAS
USB_VBUS
DMFS, DMHS
DPFS, DPHS
MCKO
MDO[5..0]
MSEO[1..0]
EVTI_N
EVTO_N
NEXUS
CLASS 2+
OCD
MEMORY PROTECTION UNIT
MEMORY INTERFACE
JTAG
INTERFACE
AVR32UC
CPU
INSTR
INTERFACE
DATA
INTERFACE
LOCAL BUS
INTERFACE
FAST GPIO
64 KB
SRAM
USB HS
INTERFACE
DMA
32KB RAM
32KB RAM
HRAM0/1
S
M
S
S
M
M
M
M
M
S
S
256/128/64
KB
FLASH
DMACA
S
EXTERNAL BUS INTERFACE
(SDRAM, STATIC MEMORY, COMPACT
FLASH & NAND FLASH)
HIGH SPEED
BUS MATRIX
DATA[15..0]
ADDR[23..0]
NCS[5..0]
NRD
NWAIT
NWE0
NWE1
NWE3
RAS
CAS
SDA10
SDCK
SDCKE
SDWE
CFCE1
CFCE2
CFRW
NANDOE
NANDWE
GENERAL PURPOSE IOs
AES
DMA
S
S
CONFIGURATION
S
REGISTERS BUS
M
PB
HSB
HSB
HSB-PB
BRIDGE B
HSB-PB
BRIDGE A
PB
PERIPHERAL
DMA
CONTROLLER
CLK
CMD[1..0]
PA
PB
PC
PX
DATA[15..0]
DMA
USART1
GENERAL PURPOSE IOs
MULTIMEDIA CARD
& MEMORY STICK
INTERFACE
DMA
PBA
RXD
TXD
CLK
RTS, CTS
DSR, DTR, DCD, RI
RXD
TXD
CLK
RTS, CTS
EXTINT[7..0]
SCAN[7..0]
NMI
DMA
EXTERNAL
INTERRUPT
CONTROLLER
REAL TIME
COUNTER
DMA
INTERRUPT
CONTROLLER
PA
PB
PC
PX
USART0
USART2
RXD
USART3
TXD
CLK
VDDIN
GNDCORE
VDDCORE
1V8
Regulator
SERIAL
PERIPHERAL
INTERFACE 0/1
SYNCHRONOUS
SERIAL
CONTROLLER
SPCK
MISO, MOSI
NPCS0
NPCS[3..1]
TX_CLOCK, TX_FRAME_SYNC
TX_DATA
RX_CLOCK, RX_FRAME_SYNC
RX_DATA
WATCHDOG
TIMER
DMA
115 kHz
RCSYS
XIN32
XOUT32
XIN0
XOUT0
XIN1
XOUT1
POWER
MANAGER
DMA
DMA
32 KHz
OSC
OSC0
OSC1
PLL0
PLL1
TWCK
CLOCK
GENERATOR
CLOCK
CONTROLLER
SLEEP
CONTROLLER
RESET
CONTROLLER
TWO-WIRE
INTERFACE 0/1
TWD
TWALM
ANALOG TO
DIGITAL
CONVERTER
AUDIO
BITSTREAM
DAC
DMA
AD[7..0]
DMA
DATA[1..0]
DATAN[1..0]
RESET_N
GCLK[3..0]
A[2..0]
B[2..0]
CLK[2..0]
TIMER/COUNTER
0/1
4
32072H–AVR32–10/2012
AT32UC3A3
2.2
Configuration Summary
The table below lists all AT32UC3A3/A4 memory and package configurations:
Table 2-1.
Feature
Flash
SRAM
HSB RAM
EBI
GPIO
Configuration Summary
AT32UC3A3256/128/64
AT32UC3A4256/128/64
256/128/64 KB
64 KB
64 KB
Full
110
8
2
4
8
4
2
2 MMC/SD slots
1
1
1
1
6
1
1
1
PLL 80-240 MHz (PLL0/PLL1)
Crystal Oscillators 0.4-20 MHz (OSC0/OSC1)
Crystal Oscillator 32 KHz (OSC32K)
RC Oscillator 115 kHz (RCSYS)
1
8
1
84 MHz
LQFP144, TFBGA144
VFBGA100
1 MMC/SD slot
+ 1 SD slot
Nand flash only
70
External Interrupts
TWI
USART
Peripheral DMA Channels
Generic DMA Channels
SPI
MCI slots
High Speed USB
AES (S option)
SSC
Audio Bitstream DAC
Timer/Counter Channels
Watchdog Timer
Real-Time Clock Timer
Power Manager
Oscillators
10-bit ADC
number of channels
JTAG
Max Frequency
Package
5
32072H–AVR32–10/2012
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