512K x 36, 1M x 18
2.5V Synchronous ZBT™ SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs
◆
◆
IDT71T75602
IDT71T75802
Features
◆
◆
◆
◆
512K x 36, 1M x 18 memory configurations
Supports high performance system speed - 200 MHz
(3.2 ns Clock-to-Data Access)
ZBT
TM
Feature - No dead cycles between write and read
cycles
Internally synchronized output buffer enable eliminates the
need to control
OE
Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
◆
◆
◆
◆
◆
◆
◆
◆
◆
4-word burst capability (interleaved or linear)
Individual byte write (BW
1
-
BW
4
) control (May tie active)
Three chip enables for simple depth expansion
2.5V power supply (±5%)
2.5V I/O Supply (V
DDQ
)
Power down controlled by ZZ input
Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA)
Green parts available, see Ordering Information
Functional Block Diagram - 512K x 36
LBO
512Kx36 BIT
MEMORY ARRAY
Address
Address A [0:18]
CE1
,
CE2
,
CE2
R
/
W
CEN
ADV/LD
BW
x
D
Q
D
Q
Control
DI
DO
D
Input Register
Q
Clk
Control Logic
Mux
Sel
Clock
D
Output Register
Q
OE
Gate
Clk
TMS
TDI
TCK
TRST
(optional)
JTAG
TDO
Data I/O [0:31],
I/O P[1:4]
5313 drw 01
OCTOBER 2017
1
©2017 Integrated Device Technology, Inc.
DSC-5313/11
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Description
There are three chip enable pins (CE
1
, CE
2
,
CE
2
) that allow the user
The IDT71T75602/802 are 2.5V high-speed 18,874,368-bit (18 Mega- to deselect the device when desired. If any one of these three is not
bit) synchronous SRAMs. They are designed to eliminate dead bus asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be com-
cycles when turning the bus around between reads and writes, or writes
pleted. The data bus will tri-state two cycles after the chip is deselected or
and reads. Thus, they have been given the name ZBT
TM
, or Zero Bus
a write is initiated.
Turnaround.
The IDT71T75602/802 have an on-chip burst counter. In the burst
Address and control signals are applied to the SRAM during one clock
mode, the IDT71T75602/802 can provide four cycles of data for a single
cycle, and two cycles later the associated data cycle occurs, be it read or
address presented to the SRAM. The order of the burst sequence is
write.
defined by the
LBO
input pin. The
LBO
pin selects between linear and
The IDT71T75602/802 contain data I/O, address and control signal
interleaved burst sequence. The ADV/LD signal is used to load a new
registers. Output enable is the only asynchronous signal and can be used
external address (ADV/LD = LOW) or increment the internal burst
to disable the outputs at any given time.
counter (ADV/LD = HIGH).
A Clock Enable
CEN
pin allows operation of the IDT71T75602/802
The IDT71T75602/802 SRAMs utilize a high-performance 2.5V
to be suspended as long as necessary. All synchronous inputs are
CMOS process, and are packaged in a JEDEC Standard 14mm x
ignored when (CEN) is high and the internal device registers will hold their
20mm 100pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid
previous values.
array (BGA).
Functional Block Diagram - 1M x 18
LBO
1Mx18 BIT
MEMORY ARRAY
Address
Address A [0:19]
CE1
,
CE2
,
CE2
R
/
W
CEN
ADV/LD
BW
x
D
Q
D
Q
Control
DI
DO
D
Input Register
Q
Clk
Control Logic
Mux
Sel
Clock
D
Output Register
Q
OE
Gate
Clk
TMS
TDI
TCK
TRST
(optional)
JTAG
TDO
Data I/O [0:15],
I/O P[1:2]
5313 drw 01b
6.42
2
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Description Summary
A
0
-A
19
CE
1
, CE
2
,
CE
2
OE
R/W
CEN
BW
1
,
BW
2
,
BW
3
,
BW
4
CLK
ADV/LD
LBO
TMS
TDI
TCK
TDO
TRST
ZZ
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
V
DD
, V
DDQ
V
SS
Address Inputs
Chip Enables
Output Enable
Read/Write Signal
Clock Enable
Individual Byte Write Selects
Clock
Advance burst address / Load new address
Linear / Interleaved Burst Order
Test Mode Select
Test Data Input
Test Clock
Test Data Input
JTAG Reset (Optional)
Sleep Mode
Data Input / Output
Core Power, I/O Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
N/A
N/A
N/A
N/A
Asynchronous
Synchronous
Synchronous
Static
Static
5313 tbl 01
6.42
3
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Definitions
(1)
Symbol
A
0
-A
19
ADV/LD
Pin Function
Address Inputs
Advance / Load
I/O
I
I
Active
N/A
N/A
Description
Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,
ADV/LD low,
CEN
low, and true chip enables.
ADV/LD is a synchronous input that is used to load the internal registers with new address and control when it is
sampled low at the rising edge of clock with the chip selected. When ADV/LD is low with the chip deselected,
any burst in progress is terminated. When ADV/LD is sampled high then the internal burst counter is advanced
for any burst that was in progress. The external addresses are ignored when ADV/LD is sampled high.
R/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write access
to the memory array. The data bus activity for the current cycle takes place two clock cycles later.
Synchronous Clock Enable Input. When
CEN
is sampled high, all other synchronous inputs, including clock are
ignored and outputs remain unchanged. The effect of
CEN
sampled high on the device outputs is as if the low
to high clock transition did not occur. For normal operation,
CEN
must be sampled low at rising edge of clock.
Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write cycles
(when R/W and ADV/LD are sample d low) the appropriate byte write signal (BW
1
-BW
4
) must be valid. The byte
write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/
W
is sampled
high. The appropriate byte(s) of data are written into the device two cycles later.
BW
1
-BW
4
can all be tied low if
always doing write to the entire 36-bit word.
Synchronous active low chip enable.
CE
1
and
CE
2
are used with CE
2
to enable the IDT71T75602/802 (CE
1
or
CE
2
sampled high or CE
2
sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle. The
ZBT
TM
has a two cycle de select, i.e., the data bus will tri-state two clock cycles after deselect is initiated.
Synchronous active high chip enable. CE
2
is used with
CE
1
and
CE
2
to enable the chip. CE
2
has inverted polarity
but otherwise identical to
CE
1
and
CE
2
.
This is the clock input to the IDT71T75602/802. Except for
OE,
all timing references for the device are made with
respect to the rising edge of CLK.
Synchronous data input/output (I/O) pins. Both the data input path and data output path are reg istered and triggered
by the rising edge of CLK.
Burst order selection input. When
LBO
is high the Interleaved burst sequence is sele cted. When
LBO
is low the
Linear burst sequence is selected.
LBO
is a static input and it must not change during device operation.
Asynchronous output enable .
OE
must be low to read data from the 71T75602/802. Whe n
OE
is high the I/O pins
are in a high-impedance state.OE does not need to be actively controlled for read and write cycles. In normal
operation,
OE
can be tied low.
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an internal pullup.
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an internal
pullup.
Clock input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising edge of TCK, while
test outputs are d riven from the falling edge of TCK. This pin has an internal pullup.
Serial output of registers placed between TDI and TDO. This output is active depending on the state of the TAP
controller.
Optional asynchronous JTAG reset. Can be used to reset the TAP controller, but not required. JTAG reset occurs
automatically at power up and also resets using TMS and TCK per IEEE 1149.1. If not used
TRST
can be left
floating. This pin has an internal pullup. Only available in BGA package.
Synchro nous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71T75602/802 to its
lowest power consumption level. Data retention is guaranteed in Sleep Mode. This pin has an internal pulldown.
2.5V core power supply.
2.5V I/O Supply.
Ground.
5313 tbl 02
R/W
CEN
Read / Write
Clock Enable
I
I
N/A
LOW
BW
1
-BW
4
Individual Byte
Write Enables
I
LOW
CE
1
,
CE
2
Chip Enables
I
LOW
CE
2
CLK
I/O
0
-I/O
31
I/O
P1
-I/O
P4
LBO
OE
Chip Enable
Clock
Data Input/Output
Linear Burst Order
Output Enable
I
I
I/O
I
I
HIGH
N/A
N/A
LOW
LOW
TMS
TDI
TCK
TDO
Test Mode Select
Test Data Input
Test Clock
Test Data Output
JTAG Reset
(Optional)
Sleep Mode
Power Supply
Power Supply
Ground
I
I
I
O
N/A
N/A
N/A
N/A
TRST
I
LOW
ZZ
V
DD
V
DDQ
V
SS
I
N/A
N/A
N/A
HIGH
N/A
N/A
N/A
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
4
IDT71T75602, IDT71T75802, 512K x 36, 1M x 18, 2.5V Synchronous ZBT™ SRAMs with
2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Recommended DC Operating
Conditions
Symbol
V
DD
V
DDQ
V
SS
V
IH
V
IH
V
IL
Parameter
Core Supply Voltage
I/O Supply Voltage
Ground
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
Min.
2.375
2.375
0
1.7
1.7
-0.3
(1)
Typ.
2.5
2.5
0
____
____
____
Recommended Operating
Temperature and Supply Voltage
Unit
V
V
V
V
V
V
5313 tbl 03
Max.
2.625
2.625
0
V
DD
+0.3
V
DDQ
+0.3
0.7
Grade
Commercial
Industrial
Ambient
Temperature
(1)
0° C to +70° C
-40° C to +85° C
V
SS
OV
OV
V
DD
2.5V ± 5%
2.5V ± 5%
V
DDQ
2.5V ± 5%
2.5V ± 5%
5313 tbl 05
NOTE:
1. During production testing, the case temperature equals the ambient temperature.
NOTE:
1. V
IL
(min.) = –0.8V for pulse width less than t
CYC
/2, once per cycle.
Pin Configuration — 512K x 36
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
I/O
P2
I/O
15
I/O
14
V
DDQ
V
SS
I/O
13
I/O
12
I/O
11
I/O
10
V
SS
V
DDQ
I/O
9
I/O
8
V
SS
V
DD
(1)
V
DD
ZZ
I/O
7
I/O
6
V
DDQ
V
SS
I/O
5
I/O
4
I/O
3
I/O
2
V
SS
V
DDQ
I/O
1
I/O
0
I/O
P1
A
9
A
8
A
17
A
18
ADV/LD
OE
CEN
R/W
CLK
V
SS
V
DD
CE
2
BW
1
BW
2
BW
3
BW
4
CE
2
CE
1
A
7
A
6
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
2
3 4
5
6 7 8
50
49
48
47
46
45
44
43
42
41
71T75602
PKG100
40
39
38
37
36
35
34
33
32
31
A
16
A
15
A
14
A
13
A
12
A
11
A
10
NC/TCK
(2)
NC/TDO
(2)
V
DD
V
SS
NC/TDI
(2)
NC/TMS
(2)
A
0
A
1
A
2
A
3
A
4
A
5
LBO
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
5313 drw 02r
NOTES:
1. Pins 14, 16, and 66 do not have to be connected directly to V
DD
as long as the input voltage is
≥
V
IH
.
2. Pins 38, 39 and 43 will be pulled internally to V
DD
if not actively driven. To disable the TAP controller without interfering with normal operation, several settings are possible. Pins 38, 39
and 43 could be tied to V
DD
or V
SS
and pin 42 should be left unconnected. Or all JTAG inputs (TMS, TDI and TCK) pins 38, 39 and 43 could be left unconnected “NC” and the JTAG
circuit will remain disabled from power up.
I/O
P3
I/O
16
I/O
17
V
DDQ
V
SS
I/O
18
I/O
19
I/O
20
I/O
21
V
SS
V
DDQ
I/O
22
I/O
23
V
DD
(1)
V
DD
V
DD
(1)
V
SS
I/O
24
I/O
25
V
DDQ
V
SS
I/O
26
I/O
27
I/O
28
I/O
29
V
SS
V
DDQ
I/O
30
I/O
31
I/O
P4
Top View
100 TQFP
6.42
5
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