ATA6838C
Hex Half-bridge Driver with Serial Input Control
DATASHEET
Features
●
Six half-bridge outputs formed by six high-side and six low-side drivers
●
Capable of switching all kinds of loads (such as DC motors, bulbs, resistors,
capacitors and inductors)
●
R
DSon
typically 1.0 at 25°C, maximum 1.8 at 150°C
●
Up to 950-mA output current
●
Very low total quiescent current I
S
< 2µA in standby mode
●
Outputs short-circuit protected
●
Overtemperature prewarning and protection
●
Undervoltage protection
●
Various diagnosis functions such as shorted output, open load, overtemperature
and power supply fail
●
Serial data interface
●
Operation voltage up to 40V
●
Daisy chaining possible
●
Serial interface 5V compatible, up to 2MHz clock frequency
●
QFN24 5mm x 5mm power package
9237G-AUTO-02/15
1.
Description
The Atmel
®
ATA6838C is a fully protected hex half-bridge driver designed in Smart Power SOI technology, used to control
up to six different loads by a microcontroller in automotive and industrial applications.
Each of the six high-side and six low-side drivers is capable of driving currents up to 950mA. The drivers are internally
connected to form six half-bridges and can be controlled separately from a standard serial data interface. Therefore, all kinds
of loads, such as bulbs, resistors, capacitors and inductors, can be combined. The IC especially supports the application of
H-bridges to drive DC motors.
Protection is guaranteed in terms of short-circuit conditions, overtemperature and undervoltage. Various diagnosis functions
and a very low quiescent current in standby mode make a wide range of applications possible.
Automotive qualification referring to conducted interferences, EMC protection and ESD protection gives added value and
enhanced quality for the exacting requirements of automotive applications.
Figure 1-1. Block Diagram QFN24
S
I
S
C
T
O
L
D
H
S
6
L
S
6
H
S
5
L
S
5
H
S
4
L
S
4
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
L
S
1
S
R
R
3, 4
VS
Input register
Ouput register
Serial interface
Charge
pump
L
S
1
T
P
DI
19
P
S
F
I
N
H
S
C
D
H
S
6
L
S
6
H
S
5
L
S
5
H
S
4
L
S
4
H
S
3
L
S
3
H
S
2
L
S
2
H
S
1
CLK
18
CS
17
UV
protection
14
Control
logic
13
INH
12
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
VCC
Power on
reset
24
DO
GND
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
Fault
Detect
16
GND
Thermal
protection
15
GND
7
11
8
5
2
23
20
GND
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
2
ATA6838C [DATASHEET]
9237G–AUTO–02/15
2.
2.1
Pin Configuration
QFN24
Figure 2-1. Pinning QFN 24, 5
5, 0.65mm Pitch
NC
OUT5
OUT5 SENSE
OUT6 SENSE
OUT6
DI
OUT4 SENSE
OUT4
VS
VS
OUT3
OUT3 SENSE
1
2
3
4
5
6
24 23 22 21 20 19
18
17
16
15
14
13
7 8 9 10 11 12
CLK
CS
GND SENSE
NC
VCC
DO
Note:
YWW
ATAxyz
ZZZZZ
AL
Date code (Y = Year above 2000, WW = week number)
Product name
Wafer lot number
Assembly sub-lot number
Table 2-1.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
Pin Description QFN24
Symbol
OUT4
SENSE
OUT4
VS
VS
OUT3
OUT3
SENSE
NC
OUT2
OUT2
SENSE
OUT1
SENSE
OUT1
INH
Function
Only for testability in final test
Half-bridge output 4; formed by internally connected power MOS high-side switch 4 and
low-side switch 4 with internal reverse diodes; short circuit protection; overtemperature
protection; diagnosis for short and open load
Power supply output stages HS4, HS5 and HS6
Power supply output stages HS1, HS2 and HS3
Output 3; see pin 1
Only for testability in final test
Internal bond to GND
Output 2; see pin 1
Only for testability in final test
Only for testability in final test
Output 1; see pin 1
Inhibit input; 5V logic input with internal pull down; low = standby, high = normal operation
NC
OUT2
OUT2 SENSE
OUT1 SENSE
OUT1
INH
ATA6838C [DATASHEET]
9237G–AUTO–02/15
3
Table 2-1.
Pin
13
14
15
16
17
18
19
20
21
22
23
24
Pin Description QFN24 (Continued)
Symbol
DO
VCC
NC
Function
Serial data output; 5V CMOS logic level tri-state output for output (status) register data;
sends 16-bit status information to the microcontroller (LSB is transferred first). Output will
remain tri-stated unless device is selected by CS = low, therefore, several ICs can operate
on one data output line only
Logic supply voltage (5V)
Internal bond to GND
Chip select input; 5V CMOS logic level input with internal pull up;
low = serial communication is enabled, high = disabled
Serial clock input; 5V CMOS logic level input with internal pull down;
controls serial data input interface and internal shift register (f
max
= 2MHz)
Serial data input; 5V CMOS logic level input with internal pull down; receives serial data from
the control device; DI expects a 16-bit control word with LSB being transferred first
Output 6; see pin 1
Only for testability in final test
Only for testability in final test
Output 5; see pin 1
Internal bond to GND
GND SENSE Ground; reference potential; internal connection to the lead frame; cooling tab
CS
CLK
DI
OUT6
OUT6
SENSE
OUT5
SENSE
OUT5
NC
4
ATA6838C [DATASHEET]
9237G–AUTO–02/15
3.
3.1
Functional Description
Serial Interface
Data transfer starts with the falling edge of the CS signal. Data must appear at DI synchronized to CLK and is accepted on
the falling edge of the CLK signal. LSB (bit 0, SRR) has to be transferred first. Execution of new input data is enabled on the
rising edge of the CS signal. When CS is high, pin DO is in a tri-state condition. This output is enabled on the falling edge of
CS. Output data will change their state with the rising edge of CLK and stay stable until the next rising edge of CLK appears.
LSB (bit 0, TP) is transferred first.
Figure 3-1. Data Transfer Input Data Protocol
CS
DI
SRR
0
LS1
1
HS1
2
LS2
3
HS2
4
LS3
5
HS3
6
LS4
7
HS4
8
LS5
9
HS5
10
LS6
11
HS6
12
OLD
13
SCT
14
SI
15
CLK
DO
TP
SLS1
SHS1 SLS2 SHS2
SLS3 SHS3
SLS4
SHS4
SLS5
SHS5 SLS6
SHS6
SCD
INH
PSF
Table 3-1.
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Input Data Protocol
Input Register
SRR
LS1
HS1
LS2
HS2
LS3
HS3
LS4
HS4
LS5
HS5
LS6
HS6
OLD
SCT
SI
Function
Status register reset (high = reset; the bits PSF, SCD and overtemperature shutdown
in the output data register are set to low)
Controls output LS1 (high = switch output LS1 on)
Controls output HS1 (high = switch output HS1 on)
See LS1
See HS1
See LS1
See HS1
See LS1
See HS1
See LS1
See HS1
See LS1
See HS1
Open load detection (low = on)
Programmable time delay for short circuit
(shutdown delay high/low = 12ms/1.5ms)
Software inhibit; low = standby, high = normal operation
(data transfer is not affected by standby function because the digital part is still
powered)
ATA6838C [DATASHEET]
9237G–AUTO–02/15
5
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