74AUP2G57
Low-power dual PCB configurable multiple function gate
Rev. 2 — 2 December 2015
Product data sheet
1. General description
The 74AUP2G57 is a dual configurable multiple function gate with Schmitt-trigger inputs.
Each gate within the device can be configured as any of the following logic functions AND,
OR, NAND, NOR, XNOR, inverter and buffer; using the 3-bit input. All inputs can be
connected directly to V
CC
or GND.
This device ensures very low static and dynamic power consumption across the entire
V
CC
range from 0.8 V to 3.6 V.
This device is fully specified for partial power down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing the potentially damaging backflow current through
the device when it is powered down.
2. Features and benefits
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
ESD protection:
HBM JESD22-A114F exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Low static power consumption; I
CC
= 0.9
A
(maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10% of V
CC
I
OFF
circuitry provides partial power-down mode operation
Multiple package options
Specified from
40 C
to +85
C
and
40 C
to +125
C
Nexperia
74AUP2G57
Low-power dual PCB configurable multiple function gate
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74AUP2G57DP
74AUP2G57GU
74AUP2G57GF
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
TSSOP10
XQFN10
XSON10
Description
plastic thin shrink small outline package; 10 leads;
body width 3 mm
plastic, extremely thin quad flat package; no leads;
10 terminals; body 1.40
1.80
0.50 mm
Version
SOT552-1
SOT1160-1
Type number
plastic extremely thin small outline package; no leads; SOT1081-2
10 terminals; body 1.0
1.7
0.5 mm
4. Marking
Table 2.
Marking
Marking code
[1]
aC
aC
aC
Type number
74AUP2G57DP
74AUP2G57GU
74AUP2G57GF
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Fig 1.
Logic symbol (one gate)
74AUP2G57
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 2 December 2015
2 of 21
Nexperia
74AUP2G57
Low-power dual PCB configurable multiple function gate
6. Pinning information
6.1 Pinning
Fig 2.
Pin configuration SOT552-1 (TSSOP10)
Fig 3.
Pin configuration SOT1160-1 (XQFN10)
Fig 4.
Pin configuration SOT1081-2 (XSON10)
74AUP2G57
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 2 December 2015
3 of 21
Nexperia
74AUP2G57
Low-power dual PCB configurable multiple function gate
6.2 Pin description
Table 3.
Symbol
1A, 2A
1B, 2B
1C, 2C
1Y, 2Y
GND
V
CC
Pin description
Pin
SOT552-1 and SOT1081-2 SOT1160-1
1, 6
2, 7
3, 8
9, 4
5
10
10, 5
1, 6
2, 7
8, 3
4
9
data input
data input
data input
data output
ground (0 V)
supply voltage
Description
7. Functional description
Table 4.
Input
nC
L
L
L
L
H
H
H
H
[1]
Function table
[1]
Output
nB
L
L
H
H
L
L
H
H
nA
L
H
L
H
L
H
L
H
nY
H
L
H
L
L
L
H
H
H = HIGH voltage level; L = LOW voltage level.
7.1 Logic configurations
Table 5.
Function selection table
Figure
see
Figure 5
see
Figure 8
see
Figure 6
and
Figure 7
see
Figure 6
and
Figure 7
see
Figure 8
see
Figure 5
see
Figure 9
see
Figure 10
see
Figure 11
Logic function
2-input AND
2-input AND with both inputs inverted
2-input NAND with inverted input
2-input OR with inverted input
2-input NOR
2-input NOR with both inputs inverted
2-input XNOR
Inverter
Buffer
74AUP2G57
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 2 December 2015
4 of 21
Nexperia
74AUP2G57
Low-power dual PCB configurable multiple function gate
Pin numbers are not valid for SOT1160-1 package
Pin numbers are not valid for SOT1160-1 package
Fig 5.
2-input AND gate or 2-input NOR gate with
both inputs inverted
Fig 6.
2-input NAND gate with input B inverted or
2-input OR gate with inverted C input
Pin numbers are not valid for SOT1160-1 package
Pin numbers are not valid for SOT1160-1 package
Fig 7.
2-input NAND gate with input C inverted or
2-input OR gate with inverted A input
Fig 8.
2-input NOR gate or 2-input AND gate with
both inputs inverted
Pin numbers are not valid for SOT1160-1 package
Pin numbers are not valid for SOT1160-1 package
Fig 9.
2-input XNOR gate
Fig 10. Inverter
Pin numbers are not valid for SOT1160-1 package
Fig 11. Buffer
74AUP2G57
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 2 — 2 December 2015
5 of 21
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