Features
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80C52 Compatible
– 8051 Instruction Compatible
– Four 8-bit I/O Ports (44 Pins Version)
– Three 16-bit Timer/Counters
– 256 bytes Scratch Pad RAM
– 11 Interrupt Sources With 4 Priority Levels
ISP (In-System Programming) Using Standard V
CC
Power Supply
Integrated Power Monitor (POR/PFD) to Supervise Internal Power Supply
Boot ROM Contains Serial Loader for In-System Programming
High-speed Architecture
– In Standard Mode:
40 MHz (Vcc 2.7V to 5.5V, Both Internal and External Code Execution)
60 MHz (Vcc 4.5V to 5.5V and Internal Code Execution Only)
– In X2 Mode (6 Clocks/Machine Cycle)
20 MHz (Vcc 2.7V to 5.5V, Both Internal and External Code Execution)
30 MHz (Vcc 4.5V to 5.5V and Internal Code Execution Only)
128K bytes On-chip Flash Program/Data Memory
– 128 bytes Page Write with auto-erase
– 100k Write Cycles
On-chip 8192 bytes Expanded RAM (XRAM)
– Software Selectable Size (0, 256, 512, 768, 1024, 1792, 2048, 4096, 8192 bytes)
Dual Data Pointer
Extended stack pointer to 512 bytes
Variable Length MOVX for Slow RAM/Peripherals
Improved X2 Mode with Independant Selection for CPU and Each Peripheral
Keyboard Interrupt Interface on Port 1
SPI Interface (Master/Slave Mode)
8-bit Clock Prescaler
Programmable Counter Array with:
– High Speed Output
– Compare/Capture
– Pulse Width Modulator
– Watchdog Timer Capabilities
Asynchronous Port Reset
Two Full Duplex Enhanced UART with Dedicated Internal Baud Rate Generator
Low EMI (inhibit ALE)
Hardware Watchdog Timer (One-time Enabled with Reset-Out), Power-Off Flag
Power Control Modes: Idle Mode, Power-down Mode
Power Supply: 2.7V to 5.5V
Temperature Ranges: Industrial (-40 to +85°C)
Packages: PLCC44, VQFP44
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8-bit Flash
Microcontroller
AT89C51RE2
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Description
AT89C51RE2 is a high performance CMOS Flash version of the 80C51 CMOS single chip 8-bit
microcontroller. It contains a 128 Kbytes Flash memory block for program.
The 128 Kbytes Flash memory can be programmed either in parallel mode or in serial mode with
the ISP capability or with software. The programming voltage is internally generated from the
standard V
CC
pin.
The AT89C51RE2 retains all features of the Atmel 80C52 with 256 bytes of internal RAM, a 10-
source 4-level interrupt controller and three timer/counters.
In addition, the AT89C51RE2 has a Programmable Counter Array, an XRAM of 8192 bytes, a
Hardware Watchdog Timer, SPI and Keyboard, two serial channels that facilitates multiproces-
sor communication (EUART), a speed improvement mechanism (X2 mode) and an extended
stack mode that allows the stack to be extended in the lower 256 bytes of XRAM.
The fully static design of the AT89C51RE2 allows to reduce system power consumption by
bringing the clock frequency down to any value, even DC, without loss of data.
The AT89C51RE2 has 2 software-selectable modes of reduced activity and 8-bit clock prescaler
for further reduction in power consumption. In the Idle mode the CPU is frozen while the periph-
erals and the interrupt system are still operating. In the power-down mode the RAM is saved and
all other functions are inoperative.
The added features of the AT89C51RE2 make it more powerful for applications that need pulse
width modulation, high speed I/O and counting capabilities such as alarms, motor control,
corded phones, smart card readers.
Table 1.
Memory Size and I/O pins
AT89C51RE2
PLCC44
VQFP44
Flash (bytes)
128K
XRAM (bytes)
8192
TOTAL RAM (bytes)
8192 + 256
I/O
34
2
AT89C51RE2
7663E–8051–10/08
AT89C51RE2
Block Diagram
Figure 1.
Block Diagram
Keyboard
RxD_0
RxD_1
(1)
BOOT Regulator
4K x8 POR / PFD
ROM
TxD_0
T2EX
VCC
PCA
Vss
TxD_1
ECI
T2
(2) (2)
XTALA1
XTALA2
XTALB1(1)
XTALB2
ALE/ PROG
PSEN
EA
RD
WR
(2)
(2)
Timer 0
Timer 1
INT
Ctrl
CPU
C51
CORE
(1)
(1) (1)
(1)
(3) (3)
EUART
RAM
256x8
Flash
128Kx8
XRAM
8192 x 8
PCA
Watch
Dog
Timer2 Keyboard
POR
PFD
EUART_1
IB-bus
Parallel I/O Ports &
External Bus
Port 0 Port 1
Port 2
Port 3 Port4 Port 5
TWI
SPI
(2) (2)
RESET
T0
T1
(2) (2)
P1
P2
P0
P3
INT0
INT1
P4
P5
(1) (1) (1)(1)
SDA
SCL
MISO
MOSI
SCK
SS
(1): Alternate function of Port 1
(2): Alternate function of Port 3
(3): Alternate function of Port 6
3
7663E–8051–10/08
Pin Configurations
P1.1/T2EX/SS
P1.4/CEX1
P1.3/CEX0
6 5 4 3 2 1 44 43 42 41 40
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7/CEx4/MOSI
RST
P3.0/RxD_0
P6.0/RxD_1/SDA
P3.1/TxD_0
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
P6.1/TxD_1/SCL
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
P0.2/AD2
P0.3/AD3
35
34
33
32
31
30
29
P2.3/A11
P2.4/A12
P0.0/AD0
P2.1/A9
AT89C51RE2
PLCC44
18 19 20 21 22 23 24 25 26 27 28
P3.6/WR
Tx_OCD
P2.0/A8
P2.2/A10
P3.7/RD
XTAL2
XTAL1
VSS
P0.1/AD1
P1.2/ECI
Rx_OCD
P1.0/T2
VCC
P1.0/T2/XTALB1
P1.1/T2EX/SS
P1.4/CEX1
P1.3/CEX0
P0.0/AD0
P0.1/AD1
P0.2/AD2
44 43 42 41 40 39 38 37 36 35 34
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7/CEX4/MOSI
RST
P3.0/RxD_0
P6.0/RxD_1/SDA
P3.1/TxD_0
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
P6.1/TxD_1/SCL
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
AT89C51RE2
P0.3/AD3
29
28
27
26
25
24
23
Rx_OCD
P1.2/ECI
VQFP44
12 13 14 15 16 17 18 19 20 21 22
P2.3/A11
P2.4/A12
XTAL1
P3.6/WR
Tx_OCD
P2.0/A8
P3.7/RD
P2.2/A10
P2.1/A9
XTAL2
VSS
4
AT89C51RE2
7663E–8051–10/08
VCC
AT89C51RE2
Table 2.
Pin Description
Pin Number
Mnemonic
V
SS
Vss1
V
CC
P0.0-P0.7
44
43-36
LCC
22
VQFP 1.4
16
39
38
37-30
Type
I
I
I
I/O
Name and Function
Ground:
0V reference
Optional Ground:
Contact the Sales Office for ground connection.
Power Supply:
This is the power supply voltage for normal, idle and power-down operation
Port 0:
Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them
float and can be used as high impedance inputs. Port 0 must be polarized to V
CC
or V
SS
in
order to prevent any parasitic current consumption. Port 0 is also the multiplexed low-order
address and data bus during access to external program and data memory. In this
application, it uses strong internal pull-up when emitting 1s. Port 0 also inputs the code bytes
during EPROM programming. External pull-ups are required during program verification
during which P0 outputs the code bytes.
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
Port 1 pins that are externally pulled low will source current because of the internal pull-ups.
Port 1 also receives the low-order address byte during memory programming and
verification.
Alternate functions for TSC8x54/58 Port 1 include:
2
3
4
5
6
7
8
9
P2.0-P2.7
24-31
40
41
42
43
44
1
2
3
18-25
I/O
I
I
I/O
I/O
I/O
I/O
I/O
I/O
T2 (P1.0):
Timer/Counter 2 external count input/Clockout
T2EX (P1.1):
Timer/Counter 2 Reload/Capture/Direction Control
ECI (P1.2):
External Clock for the PCA
CEX0 (P1.3):
Capture/Compare External I/O for PCA module 0
CEX1 (P1.4):
Capture/Compare External I/O for PCA module 1
CEX2 (P1.5):
Capture/Compare External I/O for PCA module 2
CEX3 (P1.6):
Capture/Compare External I/O for PCA module 3
CEX4 (P1.7):
Capture/Compare External I/O for PCA module 4
Port 2:
Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
Port 2 pins that are externally pulled low will source current because of the internal pull-ups.
Port 2 emits the high-order address byte during fetches from external program memory and
during accesses to external data memory that use 16-bit addresses (MOVX @DPTR).In this
application, it uses strong internal pull-ups emitting 1s. During accesses to external data
memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
Some Port 2 pins receive the high order address bits during EPROM programming and
verification:
P2.0 to P2.5 for RB devices
P2.0 to P2.6 for RC devices
P2.0 to P2.7 for RD devices.
P3.0-P3.7
11,
13-19
5,
7-13
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s
written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs,
Port 3 pins that are externally pulled low will source current because of the internal pull-ups.
Port 3 also serves the special features of the 80C51 family, as listed below.
RXD_0 (P3.0):
Serial input port
TXD_0 (P3.1):
Serial output port
INT0 (P3.2):
External interrupt 0
P1.0-P1.7
2-9
40-44
1-3
I/O
11
13
14
5
7
8
I
O
I
5
7663E–8051–10/08
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