MC14040B
12-Bit Binary Counter
The MC14040B 12−stage binary counter is constructed with MOS
P−Channel and N−Channel enhancement mode devices in a single
monolithic structure. This part is designed with an input wave shaping
circuit and 12 stages of ripple−carry binary counter. The device
advances the count on the negative−going edge of the clock pulse.
Applications include time delay circuits, counter controls, and
frequency−driving circuits.
Features
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•
•
•
•
•
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Fully Static Operation
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low−power TTL Loads or One
Low−power Schottky TTL Load Over the Rated Temperature
Range
Common Reset Line
Pin−for−Pin Replacement for CD4040B
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
SOIC−16
D SUFFIX
CASE 751B
SOEIAJ−16
F SUFFIX
CASE 966
TSSOP−16
DT SUFFIX
CASE 948F
PIN ASSIGNMENT
Q12
Q6
Q5
Q7
Q4
Q3
Q2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
Q11
Q10
Q8
Q9
R
C
Q1
MAXIMUM RATINGS
(Voltages Referenced to V
SS
)
Symbol
V
DD
V
in
, V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation, per Package
(Note 1)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8−Second Soldering)
Value
−0.5 to +18.0
−0.5 to V
DD
+ 0.5
±10
500
−55 to +125
−65 to +150
260
Unit
V
V
16
mA
mW
°C
°C
°C
1
V
SS
MARKING DIAGRAMS
16
14040BG
AWLYWW
1
SOIC−16
16
14
040B
ALYW
G
G
1
TSSOP−16
A
WL, L
YY, Y
WW, W
G or
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
SOEIAJ−16
MC14040B
ALYWG
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
≤
(V
in
or V
out
)
≤
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 11
Publication Order Number:
MC14040B/D
MC14040B
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
−55_C
Characteristic
Output Voltage
V
in
= V
DD
or 0
“0” Level
Symbol
V
OL
V
DD
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
“1” Level
(V
O
= 0.5 or 4.5 Vdc)
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
Output Drive Current
(V
OH
= 2.5 Vdc)
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
(V
OL
= 0.4 Vdc)
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
Input Current
Input Capacitance
(V
in
= 0)
Quiescent Current
(Per Package)
Total Supply Current (Notes 3 & 4)
(Dynamic plus Quiescent,
Per Package)
(C
L
= 50 pF on all outputs, all
buffers switching)
I
OH
Source
5.0
5.0
10
15
I
OL
5.0
10
15
15
−
5.0
10
15
5.0
10
15
–3.0
–0.64
–1.6
–4.2
0.64
1.6
4.2
−
−
−
−
−
−
−
−
−
−
−
−
±0.1
−
5.0
10
20
–2.4
–0.51
–1.3
–3.4
0.51
1.3
3.4
−
−
−
−
−
–4.2
–0.88
–2.25
–8.8
0.88
2.25
8.8
±0.00001
5.0
0.005
0.010
0.015
−
−
−
−
−
−
−
±0.1
7.5
5.0
10
20
–1.7
–0.36
–0.9
–2.4
0.36
0.9
2.4
−
−
−
−
−
−
−
−
−
−
−
−
±1.0
−
150
300
600
mAdc
V
IH
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
mAdc
Min
−
−
−
4.95
9.95
14.95
−
−
−
Max
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
Min
−
−
−
4.95
9.95
14.95
−
−
−
25_C
Typ
(Note 2)
0
0
0
5.0
10
15
2.25
4.50
6.75
Max
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
125_C
Min
−
−
−
4.95
9.95
14.95
−
−
−
Max
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
Vdc
Unit
Vdc
“1” Level
V
in
= 0 or V
DD
Input Voltage
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
“0” Level
V
OH
Vdc
V
IL
Vdc
Sink
I
in
C
in
I
DD
mAdc
pF
mAdc
I
T
I
T
= (0.42
mA/kHz)
f + I
DD
I
T
= (0.85
mA/kHz)
f + I
DD
I
T
= (1.43
mA/kHz)
f + I
DD
mAdc
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
I
T
(C
L
) = I
T
(50 pF) + (C
L
– 50) Vfk
where: I
T
is in
mA
(per package), C
L
in pF, V = (V
DD
– V
SS
) in volts, f in kHz is input frequency, and k = 0.001.
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MC14040B
1
CLOCK
RESET
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
2
4
8
16
32
64
128
256
512
1024
2048
4096
Figure 3. Timing Diagram
APPLICATIONS INFORMATION
TIME−BASE GENERATOR
A 60 Hz sinewave obtained through a 1.0 Megohm
resistor connected directly to a standard 120 Vac power line
is applied to the clock input of the MC14040B. By selecting
outputs Q5, Q10, Q11, and Q12 division by 3600 is
accomplished. The MC14012B decodes the counter
outputs, produces a single output pulse, and resets the binary
counter. The resulting output frequency is 1.0 pulse/minute.
V
CC
1/6 of HC14A
1.0M
≥20pF
V
CC
MC14040B
Clock
Q5
13
12
8
1
2
4
5
120Vac
60Hz
Q10
10
Q11
9
Q12
1/2
14012B
1/2
14012B
1.0 Pulse/Minute
Output
6
NOTE:
Ground MUST be isolated
by a transformer or
opto−isolator for safety
reasons.
Figure 4. Time−Base Generator
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