SAM3N Series
Atmel | SMART ARM-based MCU
DATASHEET
Description
The Atmel
®
| SMART SAM3N series is a member of a family of Flash
microcontrollers based on the high performance 32-bit ARM
®
Cortex
®
-M3 RISC
processor. It operates at a maximum speed of 48 MHz and features up to
256 Kbytes of Flash and up to 24 Kbytes of SRAM. The peripheral set includes 2
USARTs, 2 UARTs, 2 TWIs, 3 SPIs, as well as a PWM timer, two 3-channel
general-purpose 16-bit timers, an RTC, a 10-bit ADC, and a 10-bit DAC.
The SAM3N devices have three software-selectable low-power modes: Sleep,
Wait and Backup. In Sleep mode, the processor is stopped while all other
functions can be kept running. In Wait mode, all clocks and functions are stopped
but some peripherals can be configured to wake up the system based on
predefined conditions. In Backup mode, only the RTC, RTT, 256-bit GPBR, and
wake-up logic are running.
The Real-time Event Managment allows peripherals to receive, react to and send
events in Active and Sleep modes without processor intervention.
The SAM3N series is ready for capacitive touch thanks to the Atmel QTouch
®
library, offering an easy way to implement buttons, wheels and sliders.
The SAM3N device is an entry-level general purpose microcontroller. That makes
t h e S A M 3 N t h e i d e a l s t a r t i n g p o i n t t o m o v e f r o m 8 - / 1 6 - b i t t o 3 2 - b it
microcontrollers.
It operates from 1.62V to 3.6V and is available in 48-pin, 64-pin and 100-pin QFP,
48-pin and 64-pin QFN, and 100-pin BGA packages.
The SAM3N series is the ideal migration path from the SAM3S for applications
that require a reduced BOM cost. The SAM3N series is pin-to-pin compatible with
the SAM3S series. Its aggressive price point and high level of integration pushes
its scope of use far into cost-sensitive, high-volume applications.
Atmel-11011C-ATARM-SAM3N-Series-Datasheet_16-Apr-15
1.
Features
Core
̶
ARM Cortex-M3 revision 2.0 running at up to 48 MHz
̶
Thumb
®
-2 Instruction Set
̶
24-bit SysTick Counter
̶
Nested Vector Interrupt Controller
Pin-to-pin compatible with SAM7S legacy products (48/64-pin versions) and SAM3S (48/64/100-pin versions)
Memories
̶
From 16 to 256 Kbytes embedded Flash, 128-bit wide access, memory accelerator, single plane
̶
From 4 to 24 Kbytes embedded SRAM
̶
16 Kbytes ROM with embedded bootloader routines (UART) and IAP routines
System
̶
Embedded voltage regulator for single supply operation
̶
Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe operation
̶
Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with Failure Detection and optional low power
32.768 kHz for RTC or device clock
̶
High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz default frequency for device startup.
In-application trimming access for frequency adjustment
̶
Slow Clock Internal RC oscillator as permanent low-power mode device clock
̶
One PLL up to 130 MHz for device clock
̶
Up to 10 Peripheral DMA (PDC) channels
Low Power Modes
̶
Sleep, Wait, and Backup modes, down to 1.2 µA in Backup mode with RTC, RTT, and 256-bit GPBR
Peripherals
̶
Up to 2 USARTs with RS-485 and SPI mode support. One USART (USART0) has ISO7816, IrDA® and PDC
support in addition
̶
Two 2-wire UARTs
̶
Two 2-wire Interfaces (I2C compatible)
̶
One SPI
̶
Up to two 3-channel 16-bit Timer Counters with capture, waveform, compare and PWM mode, Quadrature
Decoder Logic and 2-bit Gray Up/Down Counter for Stepper Motor
̶
4-channel 16-bit PWM
̶
32-bit low-power Real-time Timer (RTT)
̶
Low-power Real-time Clock (RTC) with calendar and alarm features
̶
Up to 16 channels, 384 ksps 10-bit ADC
̶
One 500 ksps 10-bit DAC
̶
Register Write Protection
I/O
̶
Up to 79 I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and on-
die Series Resistor Termination
̶
Three 32-bit Parallel Input/Output Controllers
Packages
̶
100-lead LQFP – 14 x 14 mm, pitch 0.5 mm
̶
100-ball TFBGA – 9 x 9 mm, pitch 0.8 mm
̶
64-lead LQFP – 10 x 10 mm, pitch 0.5 mm
̶
64-pad QFN – 9 x 9 mm, pitch 0.5 mm
̶
48-lead LQFP – 7 x 7 mm, pitch 0.5 mm
̶
48-pad QFN – 7 x 7 mm, pitch 0.5 mm
2
SAM3N Series [DATASHEET]
Atmel-11011C-ATARM-SAM3N-Series-Datasheet_16-Apr-15
1.1
Configuration Summary
The SAM3N series devices differ in memory size, package and features list.
Table 1-1
summarizes the
configurations.
Table 1-1.
Device
SAM3N4A
SAM3N4B
SAM3N4C
SAM3N2A
SAM3N2B
SAM3N2C
SAM3N1A
SAM3N1B
SAM3N1C
SAM3N0A
SAM3N0B
SAM3N0C
SAM3N00A
SAM3N00B
Notes:
Configuration Summary
Flash
(Kbytes)
256
256
256
128
128
128
64
64
64
32
32
32
16
16
SRAM
(Kbytes)
24
24
24
16
16
16
8
8
8
8
8
8
4
4
Package
LQFP48
QFN48
LQFP64
QFN64
LQFP100
BGA100
LQFP48
QFN48
LQFP64
QFN64
LQFP100
BGA100
LQFP48
QFN48
LQFP64
QFN64
LQFP100
BGA100
LQFP48
QFN48
LQFP64
QFN64
LQFP100
BGA100
LQFP48
QFN48
LQFP64
QFN64
Number
of PIOs
34
47
79
34
47
79
34
47
79
34
47
79
34
47
ADC
Channels
8
10
16
8
10
16
8
10
16
8
10
16
8
10
Timer
Channels
6
(1)
6
(2)
6
6
(1)
6(
(2)
6
6
(1)
6
(2)
6
6
(1)
6
(2)
6
6
(1)
6
(2)
PDC
Channels
8
10
10
8
10
10
8
10
10
8
10
10
8
10
USART
1
2
2
1
2
2
1
2
2
1
2
2
1
2
DAC
_
1
1
_
1
1
_
1
1
_
1
1
_
1
1. Only two TC channels are accessible through the PIO.
2. Only three TC channels are accessible through the PIO.
SAM3N Series [DATASHEET]
Atmel-11011C-ATARM-SAM3N-Series-Datasheet_16-Apr-15
3
2.
SAM3N Block Diagram
Figure 2-1.
SAM3N 100-pin version Block Diagram
TD
TDI
O
TM /TR
S A
TC /SW CE
K/ D SW
SW IO O
CL
K
L
SE
N
AG
VD
System Controller
TST
PCK0–PCK2
Voltage
Regulator
JTAG & Serial Wire
PMC
PLL
XIN
XOUT
Oscillator
3-20 MHz
WDT
RC Osc.
12/8/4 MHz
In-circuit Emulator
24-bit
N
SysTick Counter
V
Cortex-M3 Processor
I
f
max
48 MHz
C
I/D
S
SM
WKUP0–15
SUPC
Osc 32k
RC 32k
256-bit
GPBR
RTT
RTC
POR
XIN32
XOUT32
ERASE
Flash
256 Kbytes
128 Kbytes
64 Kbytes
32 Kbytes
16 Kbytes
24 Kbytes
16 Kbytes
8 Kbytes
4 Kbytes
VD
JT
SRAM
DO
DI
UT
ROM
16 Kbytes
3-layer AHB Bus Matrix f
max
48 MHz
VDDIO
NRST
RSTC
Peripheral
Bridge
PIOA
PIOB
PIOC
VDDCORE
URXD0
UTXD0
URXD1
UTXD1
UART0
UART1
PDC
Timer Counter 0
TC[0..2]
TCLK[0:2]
TIOA[0:2]
TIOB[0:2]
RXD0
TXD0
SCK0
RTS0
CTS0
RXD1
TXD1
SCK1
RTS1
CTS1
USART0
PDC
Timer Counter 1
TC[3..5]
TCLK[3:5]
TIOA[3:5]
TIOB[3:5]
USART1
PDC
SPI
PWM[0:3]
PWM
NPCS0
NPCS1
NPCS2
NPCS3
MISO
MOS
SPCK
TWCK0
TWD0
ADTRG
AD[0..15]
ADVREF
DAC0
DATRG
PDC
10-bit ADC
PDC
TWI0
TWI1
10-bit DAC
PDC
TWCK1
TWD1
Real-Time Event
4
SAM3N Series [DATASHEET]
Atmel-11011C-ATARM-SAM3N-Series-Datasheet_16-Apr-15
Figure 2-2.
SAM3N 64-pin version Block Diagram
TD
TDI
O
TM /TR
S A
TC /SW CE
K/ D SW
SW IO O
CL
K
L
SE
N
AG
VD
System Controller
TST
PCK0–PCK2
Voltage
Regulator
JTAG & Serial Wire
PMC
PLL
XIN
XOUT
Oscillator
3-20 MHz
WDT
RC Osc.
12/8/4 MHz
In-circuit Emulator
24-bit
N
SysTick Counter
V
Cortex-M3 Processor
I
f
max
48 MHz
C
I/D
S
SM
WKUP0–15
SUPC
Osc 32k
RC 32k
256-bit
GPBR
RTT
RTC
POR
XIN32
XOUT32
ERASE
Flash
256 Kbytes
128 Kbytes
64 Kbytes
32 Kbytes
16 Kbytes
24 Kbytes
16 Kbytes
8 Kbytes
4 Kbytes
VD
JT
SRAM
DO
DI
UT
ROM
16 Kbytes
3-layer AHB Bus Matrix
max
48
48 MHz
3- layer AHB Bus Matrix
f
fmax
MHz
VDDIO
NRST
RSTC
Peripheral
Bridge
PIOA
PIOB
VDDCORE
URXD0
UTXD0
URXD1
UTXD1
UART0
UART1
PDC
Timer Counter 0
TC[0..2]
TCLK[0:2]
TIOA[0:2]
TIOB[0:2]
RXD0
TXD0
SCK0
RTS0
CTS0
RXD1
TXD1
SCK1
RTS1
CTS1
USART0
PDC
Timer Counter 1
TC[3..5]
USART1
PDC
SPI
PWM[0:3]
PWM
NPCS0
NPCS1
NPCS2
NPCS3
MISO
MOS
SPCK
TWCK0
TWD0
ADTRG
AD[0..9]
ADVREF
DAC0
DATRG
PDC
10-bit ADC
PDC
TWI0
TWI1
10-bit DAC
PDC
TWCK1
TWD1
Real-Time Event
SAM3N Series [DATASHEET]
Atmel-11011C-ATARM-SAM3N-Series-Datasheet_16-Apr-15
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
