DATASHEET
LOW SKEW 1 TO 4 CLOCK BUFFER
Description
The ICS553 is a low skew, single input to four output,
clock buffer. Part of IDT’s ClockBlocks
TM
family, this is
our lowest skew, small clock buffer.
See the ICS552-02 for a 1 to 8 low skew buffer. For
more than eight outputs, see the MK74CBxxx
Buffalo
TM
series of clock drivers.
IDT makes many non-PLL and PLL based low skew
output devices as well as Zero Delay Buffers to
synchronize clocks. Contact us for all of your clocking
needs.
ICS553
Features
•
•
•
•
•
•
•
•
Extremely low skew outputs (50 ps maximum)
Packaged in 8-pin SOIC
Pb (lead) free package
Low power CMOS technology
Operating voltages of 2.5 V to 5 V
Output Enable pin tri-states outputs
5 V tolerant input clock
Commercial (0 to +70°C) and Industrial (-40 to
+85°C) temperature ranges available
Block Diagram
Q0
Q1
ICLK
Q2
Q3
Output Enable
IDT®
LOW SKEW 1 TO 4 CLOCK BUFFER
1
ICS553
REV N 051310
ICS553
LOW SKEW 1 TO 4 CLOCK BUFFER
FAN OUT BUFFER
Pin Assignment
V DD
Q0
Q1
GN D
1
2
3
4
8 - p i n S OI C
8
7
6
5
OE
Q3
Q2
I CL K
Pin Descriptions
Pin
Pin
Number Name
1
2
3
4
5
6
7
8
VDD
Q0
Q1
GND
ICLK
Q2
Q3
OE
Pin
Type
Power
Output
Output
Power
Input
Output
Output
Input
Clock output 0.
Clock output 1.
Connect to ground.
Clock input, 5 V tolerant input.
Clock Output 2.
Clock Output 3.
Pin Description
Connect to +2.5 V, +3.3 V or +5.0 V.
Output Enable. Tri-states outputs when low. Connect to VDD for normal operation.
External Components
A minimum number of external components are required for proper operation. A decoupling capacitor of
0.01 µF should be connected between VDD on pin 1 and GND on pin 4, as close to the device as possible.
A 33
Ω
series terminating resistor may be used on each clock output if the trace is longer than 1 inch.
To achieve the low output skew that the ICS553 is capable of, careful attention must be paid to board
layout. Essentially, all four outputs must have identical terminations, identical loads and identical trace
geometries. If they do not, the output skew will be degraded. For example, using a 30
Ω
series termination
on one output (with 33
Ω
on the others) will cause at least 15 ps of skew.
IDT®
LOW SKEW 1 TO 4 CLOCK BUFFER
2
ICS553
REV N 051310
ICS553
LOW SKEW 1 TO 4 CLOCK BUFFER
FAN OUT BUFFER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS553. These ratings, which
are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
Output Enable and All Outputs
ICLK
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
-0.5 V to 5.5 V
0 to +70
°
C
-40 to +85
°
C
-65 to +150
°
C
125
°
C
260
°
C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Power Supply Voltage (measured in respect to GND)
Min.
0
-40
+2.375
Typ.
Max.
+70
+85
+5.25
Units
°
C
°
C
V
DC Electrical Characteristics
VDD=2.5 V ±5%
, Ambient temperature -40 to +85
°
C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage, ICLK
Input Low Voltage, ICLK
Input High Voltage, OE
Input Low Voltage, OE
Output High Voltage
Output Low Voltage
Operating Supply Current
Nominal Output Impedance
Input Capacitance
Short Circuit Current
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
IDD
Z
O
C
IN
I
OS
Conditions
Note 1
Note 1
Min.
2.375
VDD/2+0.5
1.8
Typ.
Max.
2.625
5.5
VDD/2-0.5
VDD
0.7
Units
V
V
V
V
V
V
V
mA
Ω
I
OH
= -16 mA
I
OL
= 16 mA
No load, 135 MHz
ICLK, OE pin
2
0.4
25
20
5
±28
pF
mA
IDT®
LOW SKEW 1 TO 4 CLOCK BUFFER
3
ICS553
REV N 051310
ICS553
LOW SKEW 1 TO 4 CLOCK BUFFER
FAN OUT BUFFER
DC Electrical Characteristics (continued)
VDD=3.3 V ±5%
, Ambient temperature -40 to +85
°
C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage, ICLK
Input Low Voltage, ICLK
Input High Voltage, OE
Input Low Voltage, OE
Output High Voltage
Output Low Voltage
Output High Voltage (CMOS
Level)
Operating Supply Current
Nominal Output Impedance
Input Capacitance
Short Circuit Current
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
IDD
Z
O
C
IN
I
OS
Conditions
Note 1
Note 1
Min.
3.15
VDD/2+0.7
2
Typ.
Max.
3.45
5.5
VDD/2-0.7
VDD
0.8
Units
V
V
V
V
V
V
V
V
I
OH
= -25 mA
I
OL
= 25 mA
I
OH
= -12 mA
No load, 135 MHz
ICLK, OE pin
2.4
0.4
VDD-0.4
35
20
5
±50
mA
Ω
pF
mA
VDD=5 V ±5%
, Ambient temperature -40 to +85
°
C, unless stated otherwise
Parameter
Operating Voltage
Input High Voltage, ICLK
Input Low Voltage, ICLK
Input High Voltage, OE
Input Low Voltage, OE
Output High Voltage
Output Low Voltage
Output High Voltage (CMOS
Level)
Operating Supply Current
Nominal Output Impedance
Input Capacitance
Short Circuit Current
Symbol
VDD
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
V
OH
IDD
Z
O
C
IN
I
OS
Conditions
Note 1
Note 1
Min.
4.75
VDD/2+1
2
Typ.
Max.
5.25
5.5
VDD/2-1
VDD
0.8
Units
V
V
V
V
V
V
V
V
I
OH
= -35 mA
I
OL
= 35 mA
I
OH
= -12 mA
No load, 135 MHz
ICLK, OE pin
2.4
0.4
VDD-0.4
45
20
5
±80
mA
Ω
pF
mA
Notes: 1. Nominal switching threshold is VDD/2
IDT®
LOW SKEW 1 TO 4 CLOCK BUFFER
4
ICS553
REV N 051310
ICS553
LOW SKEW 1 TO 4 CLOCK BUFFER
FAN OUT BUFFER
AC Electrical Characteristics
VDD = 2.5 V ±5%
, Ambient Temperature -40 to +85
°
C, unless stated otherwise
Parameter
Input Frequency
Output Rise Time
Output Fall Time
Propagation Delay
Additive Period Jitter
Output to Output Skew
Device to Device Skew
Note 2
Rising edges at VDD/2
Rising edges at VDD/2
0
t
OR
t
OF
Note 1
0.8 to 2.0 V, C
L
=15 pF
2.0 to 0.8 V, C
L
=15 pF
2.2
Symbol
Conditions
Min.
0
Typ.
1.0
1.0
3
Max. Units
200
1.5
1.5
5
1
50
500
MHz
ns
ns
ns
ps
ps
ps
VDD = 3.3 V ±5%
, Ambient Temperature -40 to +85
°
C, unless stated otherwise
Parameter
Input Frequency
Output Rise Time
Output Fall Time
Propagation Delay
Additive Period Jitter
Output to Output Skew
Device to Device Skew
Note 2
Rising edges at VDD/2
Rising edges at VDD/2
0
t
OR
t
OF
Note 1
0.8 to 2.0 V, C
L
=15 pF
2.0 to 0.8 V, C
L
=15 pF
2.0
Symbol
Conditions
Min.
0
Typ.
0.6
0.6
2.4
Max. Units
200
1.0
1.0
4
1
50
500
MHz
ns
ns
ns
ps
ps
ps
VDD = 5 V ±5%
, Ambient Temperature -40 to +85
°
C, unless stated otherwise
Parameter
Input Frequency
Output Rise Time
Output Fall Time
Propagation Delay
Additive Period Jitter
Output to Output Skew
Device to Device Skew
Note 2
Rising edges at VDD/2
Rising edges at VDD/2
0
t
OR
t
OF
Note 1
0.8 to 2.0 V, C
L
=15 pF
2.0 to 0.8 V, C
L
=15 pF
1.8
Symbol
Conditions
Min.
0
Typ.
0.3
0.3
2.5
Max. Units
200
0.7
0.7
4
1
50
500
MHz
ns
ns
ns
ps
ps
ps
Notes: 1. With rail to rail input clock
2. Between any 2 outputs with equal loading.
3. Duty cycle on outputs will match incoming clock duty cycle. Consult IDT for tight duty cycle clock
generators.
IDT®
LOW SKEW 1 TO 4 CLOCK BUFFER
5
ICS553
REV N 051310
DSP 与 ARM 处理器
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