SAM4S Series
Atmel | SMART ARM-based Flash MCU
DATASHEET
Description
The Atmel
®
| SMART SAM4S series is a member of a family of Flash
microcontrollers based on the high-performance 32-bit ARM
®
Cortex
®
-M4 RISC
processor. It operates at a maximum speed of 120 MHz and features up to
2048 Kbytes of Flash, with optional dual-bank implementation and cache
memory, and up to 160 Kbytes of SRAM. The peripheral set includes a full-speed
U S B D e v ic e p o r t w i t h e m b e d d e d t r a n s c e i v e r , a h i g h - s p e e d M C I f o r
SDIO/SD/MMC, an External Bus Interface featuring a Static Memory Controller to
connect to SRAM, PSRAM, NOR Flash, LCD Module and NAND Flash, 2
USARTs, 2 UARTs, 2 TWIs, 3 SPIs, an I2S, as well as a PWM timer, two 3-
channel general-purpose 16-bit timers (with stepper motor and quadrature
decoder logic support), an RTC, a 12-bit ADC, a 12-bit DAC and an analog
comparator.
The SAM4S series is ready for capacitive touch, offering native support for the
Atmel QTouch
®
library for easy implementation of buttons, wheels and sliders.
The Atmel | SMART SAM4S devices have three software-selectable low-power
modes: Sleep, Wait and Backup. In Sleep mode, the processor is stopped while
all other functions can be kept running. In Wait mode, all clocks and functions are
stopped but some peripherals can be configured to wake up the system based on
predefined conditions. In Backup mode, only the low-power RTC and wakeup
logic are running.
The real-time event management allows peripherals to receive, react to and send
events in Active and Sleep modes without processor intervention.
The SAM4S device is a medium-range general-purpose microcontroller with the
best ratio in terms of reduced power consumption, processing power and
peripheral set. This enables the SAM4S to sustain a wide range of applications
that includes consumer, industrial control, and PC peripherals.
SAM4S devices operate from 1.62V to 3.6V.
The SAM4S series is pin-to-pin compatible with the SAM3N, SAM3S series (48-,
64- and 100-pin versions), SAM4N and SAM7S legacy series (64-pin versions).
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Downloaded from
Arrow.com.
Features
Core
̶
ARM Cortex-M4 with 2 Kbytes of cache running at up to 120 MHz
̶
Memory Protection Unit (MPU)
̶
DSP Instruction Set
̶
Thumb
®
-2 instruction set
Pin-to-pin compatible with SAM3N, SAM3S, SAM4N and SAM7S legacy products (64-pin version)
Memories
̶
Up to 2048 Kbytes embedded Flash with optional dual-bank and cache memory, ECC, Security Bit and Lock
Bits
̶
Up to 160 Kbytes embedded SRAM
̶
16 Kbytes ROM with embedded boot loader routines (UART, USB) and IAP routines
̶
8-bit Static Memory Controller (SMC): SRAM, PSRAM, NOR and NAND Flash support
System
̶
Embedded voltage regulator for single supply operation
̶
Power-on-Reset (POR), Brown-out Detector (BOD) and Watchdog for safe operation
̶
Quartz or ceramic resonator oscillators: 3 to 20 MHz main power with failure detection and optional low-power
32.768 kHz for RTC or device clock
̶
RTC with Gregorian and Persian calendar mode, waveform generation in low-power modes
̶
RTC counter calibration circuitry compensates for 32.768 kHz crystal frequency inaccuracy
̶
High-precision 8/12 MHz factory-trimmed internal RC oscillator with 4 MHz default frequency for device startup,
in-application trimming access for frequency adjustment
̶
Slow clock internal RC oscillator as permanent low-power mode device clock
̶
Two PLLs up to 240 MHz for device clock and for USB
̶
Temperature sensor
̶
Low-power tamper detection on two inputs, anti-tampering by immediate clear of general-purpose backup
registers (GPBR)
̶
Up to 22 Peripheral DMA (PDC) channels
Low-power Modes
̶
Sleep, Wait and Backup modes; consumption down to 1 µA in Backup mode
Peripherals
̶
USB 2.0 Device: 12 Mbps, 2668 byte FIFO, up to 8 bidirectional Endpoints, on-chip transceiver
̶
Up to two USARTs with ISO7816, IrDA
®
, RS-485, SPI, Manchester and Modem Mode
̶
Two 2-wire UARTs
̶
Up to two 2-Wire Interface modules (I2C-compatible), one SPI, one Serial Synchronous Controller (I2S), one
high-speed Multimedia Card Interface (SDIO/SD Card/MMC)
̶
Two 3-channel 16-bit Timer Counters with capture, waveform, compare and PWM mode, Quadrature decoder
logic and 2-bit Gray up/down counter for stepper motor
̶
4-channel 16-bit PWM with complementary output, fault input, 12-bit dead time generator counter for motor
control
̶
32-bit Real-time Timer and RTC with calendar, alarm and 32 kHz trimming features
̶
256-bit General Purpose Backup Registers (GPBR)
̶
Up to 16-channel, 1Msps ADC with differential input mode and programmable gain stage and auto calibration
̶
One 2-channel 12-bit 1Msps DAC
̶
One Analog Comparator with flexible input selection, selectable input hysteresis
̶
32-bit Cyclic Redundancy Check Calculation Unit (CRCCU) for data integrity check of off-/on-chip memories
̶
Register Write Protection
2
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Downloaded from
Arrow.com.
I/O
̶
Up to 79 I/O lines with external interrupt capability (edge or level sensitivity), debouncing, glitch filtering and on-
die series resistor termination
̶
Three 32-bit Parallel Input/Output Controllers, Peripheral DMA-assisted Parallel Capture mode
Packages
̶
100-lead packages
LQFP – 14 x 14 mm, pitch 0.5 mm
TFBGA – 9 x 9 mm, pitch 0.8 mm
VFBGA – 7 x 7 mm, pitch 0.65 mm
LQFP – 10 x 10 mm, pitch 0.5 mm
QFN – 9 x 9 mm, pitch 0.5 mm
WLCSP – 4.42 x 4.72 mm, pitch 0.4 mm (SAM4SD32/SAM4SD16)
WLCSP – 4.42 x 3.42 mm, pitch 0.4 mm (SAM4S16/S8)
WLCSP – 3.32 x 3.32 mm, pitch 0.4 mm (SAM4S4/S2)
LQFP – 7 x 7 mm, pitch 0.5 mm
QFN – 7 x 7 mm, pitch 0.5 mm
̶
64-lead packages
̶
48-lead packages
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
3
Downloaded from
Arrow.com.
Safety Features Highlight
Flash
̶
Built-in ECC (hamming), single error correction
̶
Security bit and lock bits
4
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
Downloaded from
Arrow.com.
1.
Configuration Summary
The SAM4S series devices differ in memory size, package and features.
Table 1-1
and
Table 1-2
summarize the
configurations of the device family.
Table 1-1.
Feature
Flash
SRAM
HCACHE
Configuration Summary for SAM4SD32/SD16/SA16/S16 Devices
SAM4SD32C
SAM4SD32B
SAM4SD16C
SAM4SD16B
SAM4SA16C
1024 Kbytes
160 Kbytes
2 Kbytes
LQFP100
TFBGA100
VFBGA100
79
8-bit data,
4 chip selects,
24-bit address
16 ch.
(1)
2 ch.
6
22
2/2
(3)
1 port, 4 bits
SAM4SA16B
1024 Kbytes
160 Kbytes
2 Kbytes
LQFP64
QFN64
47
–
11 ch.
(1)
2 ch.
6
(2)
22
2/2
(3)
1 port, 4 bits
SAM4S16C
1024 Kbytes
128 Kbytes
–
LQFP100
TFBGA100
VFBGA100
79
8-bit data,
4 chip selects,
24-bit address
16 ch.
(1)
2 ch.
6
22
2/2
(3)
1 port, 4 bits
SAM4S16B
1024 Kbytes
128 Kbytes
–
LQFP64
QFN64
WLCSP64
47
–
11 ch.
(1)
2 ch.
6
(2)
22
2/2
(3)
1 port, 4 bits
2 x 1024 Kbytes 2 x 1024 Kbytes 2 x 512 Kbytes 2 x 512 Kbytes
160 Kbytes
2 Kbytes
LQFP100
TFBGA100
VFBGA100
79
8-bit data,
4 chip selects,
24-bit address
16 ch.
(1)
2 ch.
6
22
2/2
(3)
1 port, 4 bits
160 Kbytes
2 Kbytes
LQFP64
QFN64
WLCSP64
47
–
11 ch.
(1)
2 ch.
6
(2)
22
2/2
(3)
1 port, 4 bits
160 Kbytes
2 Kbytes
LQFP100
TFBGA100
VFBGA100
79
8-bit data,
4 chip selects,
24-bit address
16 ch.
(1)
2 ch.
6
22
2/2
(3)
1 port, 4 bits
160 Kbytes
2 Kbytes
LQFP64
QFN64
WLCSP64
47
–
11 ch.
(1)
2 ch.
6
(2)
22
2/2
(3)
1 port, 4 bits
Package
Number of PIOs
External
Bus
Interface
12-bit ADC
12-bit DAC
Timer Counter
Channels
PDC Channels
USART/UART
HSMCI
Table 1-2.
Feature
Flash
SRAM
HCACHE
Package
Configuration Summary for SAM4S8/S4/S2 Devices
SAM4S8C
512 Kbytes
128 Kbytes
–
LQFP100
TFBGA100
VFBGA100
79
8-bit data,
4 chip selects,
24-bit address
16 ch.
(1)
2 ch.
6
22
2/2
(3)
1 port, 4 bits
SAM4S8B
512 Kbytes
128 Kbytes
–
LQFP64
QFN64
WLCSP64
47
–
11 ch.
(1)
2 ch.
6
(2)
22
2/2
(3)
1 port, 4 bits
SAM4S4C
256 Kbytes
64 Kbytes
–
LQFP100
TFBGA100
VFBGA100
79
8-bit data,
4 chip selects,
24-bit address
16 ch.
(1)
2 ch.
6
22
2/2
(3)
1 port, 4 bits
SAM4S4B
256 Kbytes
64 Kbytes
–
LQFP64
QFN64
WLCSP64
47
–
11 ch.
(1)
2 ch.
6
(2)
22
2/2
(3)
1 port, 4 bits
SAM4S4A
256 Kbytes
64 Kbytes
–
LQFP48
QFN48
34
–
8 ch.
–
6
(2)
22
2/1
–
SAM4S2C
128 Kbytes
64 Kbytes
–
LQFP100
TFBGA100
VFBGA100
79
8-bit data,
4 chip selects,
24-bit address
16 ch.
(1)
2 ch.
6
22
2/2
(3)
1 port, 4 bits
SAM4S2B
128 Kbytes
64 Kbytes
–
LQFP64
QFN64
WLCSP64
47
–
16 ch.
(1)
2 ch.
6
(2)
22
2/2
(3)
1 port, 4 bits
SAM4S2A
128 Kbytes
64 Kbytes
–
LQFP48
QFN48
34
–
8 ch
–
6
(2)
22
2/1
–
Number of PIOs
External
Bus
Interface
12-bit ADC
12-bit DAC
Timer Counter
Channels
PDC Channels
USART/UART
HSMCI
Notes:
1. One channel is reserved for internal temperature sensor.
2. Three TC channels are reserved for internal use.
3. Full modem support on USART1.
SAM4S Series [DATASHEET]
Atmel-11100K-ATARM-SAM4S-Datasheet_09-Jun-15
5
Downloaded from
Arrow.com.
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