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74LVC16374ADG-T: 产品描述Flip Flops 3.3V 16-BIT POS D-TYPE 3-S; 产品类别逻辑逻辑; 文件大小733KB，共20页; 制造商NXP(恩智浦); 官网地址https://www.nxp.com; 标准

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74LVC16374ADG-T概述

Flip Flops 3.3V 16-BIT POS D-TYPE 3-S

74LVC16374ADG-T规格参数

参数名称	属性值
Source Url Status Check Date	2013-06-14 00:00:00
是否Rohs认证	符合
厂商名称	NXP(恩智浦)
零件包装代码	TSSOP
包装说明	TSSOP, TSSOP48,.3,20
针数	48
Reach Compliance Code	unknown
系列	LVC/LCX/Z
JESD-30 代码	R-PDSO-G48
JESD-609代码	e0
长度	12.5 mm
负载电容（CL）	50 pF
逻辑集成电路类型	BUS DRIVER
最大频率@ Nom-Sup	100000000 Hz
最大I（ol）	0.024 A
位数	8
功能数量	2
端口数量	2
端子数量	48
最高工作温度	85 °C
最低工作温度	-40 °C
输出特性	3-STATE
输出极性	TRUE
封装主体材料	PLASTIC/EPOXY
封装代码	TSSOP
封装等效代码	TSSOP48,.3,20
封装形状	RECTANGULAR
封装形式	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法	TAPE AND REEL
峰值回流温度（摄氏度）	NOT SPECIFIED
电源	3.3 V
Prop。Delay @ Nom-Sup	7 ns
传播延迟（tpd）	6.4 ns
认证状态	Not Qualified
座面最大高度	1.2 mm
最大供电电压 (Vsup)	3.6 V
最小供电电压 (Vsup)	1.2 V
标称供电电压 (Vsup)	3.3 V
表面贴装	YES
技术	CMOS
温度等级	INDUSTRIAL
端子形式	GULL WING
端子节距	0.5 mm
端子位置	DUAL
处于峰值回流温度下的最长时间	NOT SPECIFIED
触发器类型	POSITIVE EDGE
宽度	6.1 mm
Base Number Matches	1

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74LVC16374A; 74LVCH16374A

16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

Rev. 11 — 16 January 2013

Product data sheet

1. General description

The 74LVC16374A and 74LVCH16374A are 16-bit edge-triggered flip-flops featuring

separate D-type inputs with bus hold (74LVCH16374A only) for each flip-flop and 3-state

outputs for bus-oriented applications. It consists of two sections of eight positive

edge-triggered flip-flops. A clock input (nCP) and an output enable (nOE) are provided for

each octal.

The flip-flops store the state of their individual D-inputs that meet the set-up and hold time

requirements on the LOW-to-HIGH clock (CP) transition.

When pin nOE is LOW, the contents of the flip-flops are available at the outputs. When pin

nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of input nOE

does not affect the state of the flip-flops.

Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be

applied to the outputs. These features allow the use of these devices in mixed 3.3 V and

5 V applications.

Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused

inputs.

2. Features and benefits



5 V tolerant inputs/outputs for interfacing with 5 V logic

Wide supply voltage range from 1.2 V to 3.6 V

CMOS low power consumption

Multibyte flow-through standard pinout architecture

Low inductance multiple supply pins for minimum noise and ground bounce

Direct interface with TTL levels

All data inputs have bus hold (74LVCH16374A only)

High-impedance outputs when V

= 0 V

Complies with JEDEC standard:



JESD8-7A (1.65 V to 1.95 V)



JESD8-5A (2.3 V to 2.7 V)



JESD8-C/JESD36 (2.7 V to 3.6 V)



ESD protection:



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-B exceeds 200 V



CDM JESD22-C101E exceeds 1000 V



Specified from

40 C

to +85

C

and

40 C

to +125

C

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