Features
•
Serial Peripheral Interface (SPI) Compatible
•
Supports SPI Modes 0 (0,0) and 3 (1,1)
•
•
•
•
•
•
•
– Datasheet Describes Mode 0 Operation
Low-voltage and Standard-voltage Operation
– 1.8 (V
CC
= 1.8V to 5.5V)
20MHz Clock Rate (5V)
32-byte Page Mode
Block Write Protection
– Protect 1/4, 1/2, or Entire Array
Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software
Data Protection
Self-timed Write Cycle (5ms max)
High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 100 Years
Green (Pb/Halide-free/RoHS Compliant) Packaging Options
Die Sales: Wafer Form, Tape and Reel, and Bumped Wafers
SPI Serial
EEPROMs
8K (1024 x 8)
16K (2048 x 8)
Atmel AT25080B
Atmel AT25160B
•
•
Description
The Atmel
®
AT25080B/160B provides 8192/16384 bits of serial electrically-erasable
programmable read-only memory (EEPROM) organized as 1024/2048 words of 8 bits
each. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The AT25080B/160B is
available in space-saving 8-lead JEDEC SOIC, 8-lead UDFN, 8-lead TSSOP, 8-lead
XDFN, and 8-ball VFBGA packages.
The AT25080B/160B is enabled through the Chip Select pin (CS) and accessed via a
three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa-
rate erase cycle is required before write.
Figure 1.
Pin Name
CS
SCK
SI
SO
GND
V
CC
WP
HOLD
Pin Configuration
Function
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Power Supply
Write Protect
Suspends Serial Input
CS
SO
WP
GND
8-lead SOIC
1
2
3
4
8
7
6
5
8-lead TSSOP
V
CC
HOLD
SCK
SI
CS
SO
WP
GND
1
2
3
4
8
7
6
5
V
CC
HOLD
SCK
SI
8-lead UDFN
V
CC
8
HOLD
7
SCK
6
SI
5
1
CS
2
SO
3
WP
4
GND
8-lead XDFN
V
CC
8
HOLD
7
SCK
6
SI
5
1
CS
2
SO
3
WP
4
GND
Bottom View
8-ball VFBGA
V
CC
HOLD
SCK
SI
8
7
6
5
1
2
3
4
Bottom View
CS
SO
WP
GND
5228E–SEEPR–3/12
Bottom View
Block write protection is enabled by programming the status register with one of four blocks of write protection.
Separate program enable and program disable instructions are provided for additional data protection. Hardware
data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The
HOLD pin may be used to suspend any serial communication without resetting the serial sequence.
2.
Absolute Maximum Ratings*
Operating Temperature ...........................–55C to +125C
Storage Temperature ..............................–65C to +150C
Voltage on Any Pin
with Respect to Ground..............................–1.0V to +7.0V
Maximum Operating Voltage.................................... 6.25V
DC Output Current .................................................. 5.0mA
*NOTICE:
Stresses beyond those listed under
“Absolute Maximum Ratings” may cause
permanent damage to the device. This is a
stress rating only and functional operation
of the device at these or any other
conditions beyond those indicated in the
operational sections of this specification is
not implied. Exposure to absolute maximum
rating conditions for extended periods may
affect device reliability.
Figure 2-1.
Block Diagram
2
AT25080B/160B
5228E–SEEPR–3/12
AT25080B/160B
Table 2-1.
Pin Capacitance
(1)
Applicable over recommended operating range from T
A
= 25C, f = 1.0MHz, V
CC
= +5.0V (unless otherwise noted)
Symbol
C
OUT
C
IN
Note:
Test Conditions
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
1. This parameter is characterized and is not 100% tested
Max
8
6
Units
pF
pF
Conditions
V
OUT
= 0V
V
IN
= 0V
Table 2-2.
DC Characteristics
Applicable over recommended operating range from: T
AI
=
–
40C to +85C, V
CC
= +1.8V to +5.5V (unless otherwise noted)
Symbol
V
CC1
V
CC2
V
CC3
I
CC1
I
CC2
I
CC3
I
SB1
I
SB2
I
SB3
I
IL
I
OL
V
IL(1)
V
IH(1)
V
OL1
V
OH1
V
OL2
V
OH2
Notes:
Parameter
Supply Voltage
Supply Voltage
Supply Voltage
Supply Current
Supply Current
Supply Current
Standby Current
Standby Current
Standby Current
Input Leakage
Output Leakage
Input Low-voltage
Input High-voltage
Output Low-voltage
Output High-voltage
Output Low-voltage
Output High-voltage
3.6V
V
CC
5.5V
1.8V
V
CC
3.6V
I
OL
= 3.0mA
I
OH
=
1.6mA
I
OL
= 0.15mA
I
OH
=
100µA
V
CC
- 0.2
V
CC
- 0.8
0.2
V
CC
= 5.0V at 20MHz, SO = Open, Read
V
CC
= 5.0V at 20MHz, SO = Open, Read,
Write
V
CC
= 5.0V at 5MHz, SO = Open,
Read, Write
V
CC
= 1.8V, CS = V
CC
V
CC
= 2.5V, CS = V
CC
V
CC
= 5.0V, CS = V
CC
V
IN
= 0V to V
CC
V
IN
= 0V to V
CC
, T
AC
= 0°C to 70°C
–3.0
–3.0
–0.6
V
CC
x 0.7
Test Condition
Min
1.8
2.5
4.5
7.5
4.0
4.0
< 0.1
0.3
2.0
Typ
Max
5.5
5.5
5.5
10.0
10.0
6.0
6.0
(2)
7.0
(2)
10.0
(2)
3.0
3.0
V
CC
x 0.3
V
CC
+ 0.5
0.4
Units
V
V
V
mA
mA
mA
µA
µA
µA
µA
µA
V
V
V
V
V
V
1. V
IL
min and V
IH
max are reference only and are not tested
2. Worst case measured at 85C
3
5228E–SEEPR–3/12
Table 2-3.
AC Characteristics
Applicable over recommended operating range from T
AI
=
–
40C to +85C, V
CC
= As Specified,
CL = 1 TTL Gate and 30pF (unless otherwise noted)
Symbol
Parameter
SCK Clock Frequency
Voltage
4.5–5.5
2.5–5.5
1.8–5.5
4.5–5.5
2.5–5.5
1.8–5.5
4.5–5.5
2.5–5.5
1.8–5.5
4.5–5.5
2.5–5.5
1.8–5.5
4.5–5.5
2.5–5.5
1.8–5.5
4.5–5.5
2.5–5.5
1.8–5.5
4.5–5.5
2.5–5.5
1.8–5.5
4.5–5.5
2.5–5.5
1.8–5.5
4.5–5.5
2.5–5.5
1.8–5.5
4.5–5.5
2.5–5.5
1.8–5.5
4.5–5.5
2.5–5.5
1.8–5.5
4.5–5.5
2.5–5.5
1.8–5.5
4.5–5.5
2.5–5.5
1.8–5.5
4.5–5.5
2.5–5.5
1.8–5.5
20
40
80
20
40
80
25
50
100
25
50
100
25
50
100
5
10
20
5
10
20
5
10
20
5
10
20
0
0
0
0
0
0
20
40
80
ns
Min
0
0
0
Max
20
10
5
2
2
2
2
2
2
Units
MHz
f
SCK
t
RI
Input Rise Time
µs
t
FI
Input Fall Time
µs
t
WH
SCK High Time
ns
t
WL
SCK Low Time
ns
t
CS
CS High Time
ns
t
CSS
CS Setup Time
ns
t
CSH
CS Hold Time
ns
t
SU
Data In Setup Time
ns
t
H
Data In Hold Time
ns
t
HD
HOLD Setup Time
t
CD
HOLD Hold Time
t
V
Output Valid
ns
t
HO
Output Hold Time
ns
4
AT25080B/160B
5228E–SEEPR–3/12
AT25080B/160B
Table 2-3.
AC Characteristics (Continued)
Applicable over recommended operating range from T
AI
=
–
40C to +85C, V
CC
= As Specified,
CL = 1 TTL Gate and 30pF (unless otherwise noted)
Symbol
Parameter
HOLD to Output Low Z
Voltage
4.5–5.5
2.5–5.5
1.8–5.5
4.5–5.5
2.5–5.5
1.8–5.5
4.5–5.5
2.5–5.5
1.8–5.5
4.5–5.5
2.5–5.5
1.8–5.5
1M
Min
0
0
0
Max
25
50
100
40
80
200
40
80
200
5
5
5
Units
ns
t
LZ
t
HZ
HOLD to Output High Z
ns
t
DIS
Output Disable Time
ns
t
WC
Endurance
(1)
Note:
Write Cycle Time
3.3V, 25°C, Page Mode
ms
Write Cycles
1. This parameter is characterized and is not 100% tested
3.
Serial Interface Description
MASTER:
The device that generates the serial clock.
SLAVE:
Because the Serial Clock pin (SCK) is always an input, the AT25080B/160B always operates as a slave.
TRANSMITTER/RECEIVER:
The AT25080B/160B has separate pins designated for data transmission (SO) and
reception (SI).
MSB:
The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE:
After the device is selected with CS going low, the first byte will be received. This byte con-
tains the op-code that defines the operations to be performed.
INVALID OP-CODE:
If an invalid op-code is received, no data will be shifted into the AT25080B/160B, and the
serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will
reinitialize the serial communication.
CHIP SELECT:
The AT25080B/160B is selected when the CS pin is low. When the device is not selected, data will
not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state.
HOLD:
The HOLD pin is used in conjunction with the CS pin to select the AT25080B/160B. When the device is
selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the mas-
ter device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is
low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle
during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state.
WRITE PROTECT:
The write protect pin (WP) will allow normal read/write operations when held high. When the
WP pin is brought low and WPEN bit is “1”, all write operations to the status register are inhibited. WP going low
while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated,
WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when
the WPEN bit in the status register is “0”. This will allow the user to install the AT25080B/160B in a system with the
WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the
WPEN bit is set to “1”.
5
5228E–SEEPR–3/12
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