Low Skew, 1-to-2 LVCMOS/ LVTTL-to-3.3V
LVPECL CLock Generator
Datasheet
8535-21
General Description
The 8535-21 is a low skew, high performance 1-to-2
LVCMOS/LVTTL-to-3.3V LVPECL fanout buffer. The 8535-21 has
two single-ended clock inputs. The single-ended clock input accepts
LVCMOS or LVTTL input levels and translate them to 3.3V LVPECL
levels. The clock enable is internally synchronized to eliminate runt
clock pulses on the output during asynchronous
assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make the
8535-21 ideal for those applications demanding well defined
performance and repeatability.
Features
•
•
•
•
•
•
•
•
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Two differential 3.3V LVPECL outputs
Selectable CLK0 or CLK1 inputs for redundant and multiple
frequency fanout applications
CLK0 or CLK1 can accept the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 266MHz
Translates LVCMOS and LVTTL levels to 3.3V LVPECL levels
Output skew: 20ps (maximum)
Part-to-part skew: 300ps (maximum)
Propagation delay: 1.6ns (maximum)
Additive phase jitter, RMS: 0.03ps (typical)
3.3V operating supply
0°C to 70°C ambient operating temperature
Industrial temperature information available upon request
Available in lead-free (RoHS 6)
Block Diagram
CLK_EN
Pullup
D
Q
CLK0
Pulludown
CLK1
Pulludown
LE
0
1
Q0
Q0
Q1
CLK_SEL
Pulludown
Q1
Pin Assignment
V
EE
CLK_EN
CLK_SEL
CLK0
V
EE
CLK1
V
CC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
Q0
Q0
nc
Q1
Q1
V
CC
8535-21
14 Lead TSSOP
4.40mm x 5.0mm x 0.925mm package body
G Package
Top View
©2015 Integrated Device Technology, Inc.
1
Revision B, December 8, 2015
8535-21 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1, 5
2
Name
V
EE
CLK_EN
Power
Input
Pullup
Type
Description
Negative supply pins.
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
When LOW, Qx outputs are forced low, Qx outputs are forced high.
LVCMOS/LVTTL interface levels.
Clock select input. When HIGH, selects CLK1 input.
When LOW, selects CLK0 input. LVCMOS/LVTTL interface levels.
Single-ended clock inputs. LVCMOS/LVTTL interface levels.
Power supply pins.
Differential output pair. LVPECL interface levels.
No connect.
Differential output pair. LVPECL interface levels.
3
4, 6
7, 8, 14
9, 10
11
12, 13
CLK_SEL
CLK0, CLK1
V
CC
Q1, Q1
nc
Q0, Q0
Input
Input
Power
Output
Unused
Output
Pulldown
Pulldown
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
©2015 Integrated Device Technology, Inc.
2
Revision B, December 8, 2015
8535-21 Datasheet
Function Tables
Table 3A. Control Input Function Table
Inputs
CLK_EN
0
0
1
1
CLK_SEL
0
1
0
1
Selected Source
CLK0
CLK1
CLK0
CLK1
Q0, Q1
Disabled; Low
Disabled; Low
Enabled
Enabled
Outputs
Q0, Q1
Disabled; High
Disabled; High
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK0 and CLK1 inputs as described in Table 3B.
Disabled
Enabled
CLK0, CLK1
CLK0, CLK1
CLK_EN
CLK_EN
Q0, Q1
nQ0, nQ1
Q0, Q1
Q0, Q1
Figure 1. CLK_EN Timing Diagram
Table 3B. Clock Input Function Table
Inputs
CLK0 or CLK1
0
1
Q0, Q1
LOW
HIGH
Outputs
Q0, Q1
HIGH
LOW
©2015 Integrated Device Technology, Inc.
3
Revision B, December 8, 2015
8535-21 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
93.2C/W (0 lfpm)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
50
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
CC
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
IH
V
IL
Parameter
Input High Voltage
CLK0, CLK1
Input Low Voltage
CLK_EN,
CLK_SEL
CLK0, CLK1,
CLK_SEL
CLK_EN
CLK0, CLK1,
CLK_SEL
CLK_EN
V
CC
= V
IN
= 3.465
V
CC
= V
IN
= 3.465
V
CC
= 465V, V
IN
= 0V
V
CC
= 465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
-0.3
-0.3
Typical
Maximum
V
CC
+ 0.3
1.3
0.8
150
5
Units
V
V
V
µA
µA
µA
µA
I
IH
Input High Current
I
IL
Input Low Current
Table 4C. LVPECL DC Characteristics,
V
CC
= 5%, T
A
= 0°C to 70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Current; NOTE 1
Output Low Current; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
– 1.4
V
CC
– 2.0
0.6
Typical
Maximum
V
CC
– 0.9
V
CC
– 1.7
1.0
Units
µA
µA
V
NOTE 1: Outputs termination with 50 to V
CC
– 2V.
©2015 Integrated Device Technology, Inc.
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Revision B, December 8, 2015
8535-21 Datasheet
AC Electrical Characteristics
Table 5. AC Characteristics,
V
CC
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
f
MAX
t
PD
tjit
tsk(o)
tsk(pp)
t
R
/ t
F
odc
Parameter
Output Frequency
Propagation Delay; NOTE 1
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section; NOTE 2
Output Skew; NOTE 3, 4
Part-to-Part Skew; NOTE 4, 5
Output Rise/Fall Time
Output Duty Cycle
20% to 80% @ 50MHz
ƒ
200MHz
300
45
ƒ
266MHz
156.25MHz, Integration Range:
12kHz – 20MHz
1.0
0.03
20
300
600
55
Test Conditions
Minimum
Typical
Maximum
266
1.6
Units
MHz
ns
ps
ps
ps
ps
%
NOTE: All parameters measured at ƒ
266MHz unless noted otherwise.
NOTE 1: Measured from V
CC
/2 of the input to the differential output crossing point. The part does not add jitter.
NOTE 2: Driving only one input clock.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V
CC
/2 of the input to the differential output crossing point.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using
the same type of inputs on each device, the outputs are measured at the differential cross points.
©2015 Integrated Device Technology, Inc.
5
Revision B, December 8, 2015
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