256K x 36, 512K x 18
3.3V Synchronous ZBT™ SRAMs
ZBT™ Feature
3.3V I/O, Burst Counter
Pipelined Outputs
◆
AS8C803601
AS8C801801
Address and control signals are applied to the SRAM during one clock
cycle, and two cycles later the associated data cycle occurs, be it read
or
write.
256K x 36, 512K x 18 memory configurations
◆
Supports high performance system speed - 150MHz
The AS8C803601/801801 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be
(3.8ns Clock-to-Data Access)
◆
ZBT
TM
Feature - No dead cycles between write and read cycles
used
to disable the outputsat any given time.
◆
Internally synchronized output buffer enable eliminates the
A Clock Enable(
CEN)
pin allows operation of the to AS8C803601/ 801801
be suspended as long as necessary. All synchronous inputs are ignored when
need to control
OE
◆
Single R/W (READ/WRITE) control pin
(CEN)is high and the internal device registers will hold their previous values.
◆
Positive clock-edge triggered address, data, and control
There are three chip enable pins (CE1, CE2,
CE2)
that allow the user
to deselect the device when desired. If any of these three are not asserted
one
signal registers for fully pipelined applications
◆
4-word burst capability (interleaved or linear)
when ADV/
LD
is low, no new memory
operation can be initiated. However,
◆
Individual byte write (BW
1
-
BW
4
) control (May tie active)
any pending data transfers (reads or writes) will be completed. The data bus
◆
Three chip enables for simple depth expansion
will tri-state two cycles after chip is deselected or a write is initiated.
◆
3.3V power supply (±5%)
TheAS8C803601/801801 have an on-chip burst counter. In the burst
◆
3.3V I/O Supply (V
DDQ
)
mode,the AS8C803601/801801 can provide fourcycles of data for a single
◆
address presented to the SRAM. The order of the burst sequence is
Power down controlled by ZZ input
◆
Packaged in a JEDEC standard 100-pin plastic thin quad
defined by the
LBO
input pin. The
LBO
pin selects between linear and
interleaved burst sequence. The ADV/
D
signal is used to load a new
L
flatpack (TQFP).
L
external address (ADV/
D
= LOW) or increment the internal burst counter
(ADV/LD = HIGH).
Description
The AS8C803601/801801 SRAM utilize IDT's latest high-performance
The AS8C803601/801801 are3.3V high-speed 9,437,184 bit
CMOS process, andare packaged ina JEDEC Standard 14mm x 20mm 100-
(9 Megabit) synchronous SRAMS. They are designed to eliminate dead bus
pin thin plastic quad flatpack (TQFP)
.
cycles when turning the bus around between reads and writes, or writes and
TM
reads. Thus, they have been given the name ZBT or Zero Bus Turnaround.
,
Features
Pin Description Summar
y
A
0
-A
18
CE
1
, CE
2
,
CE
2
OE
R/W
CEN
BW
1
,
BW
2
,
BW
3
,
BW
4
CLK
ADV/LD
LBO
ZZ
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
V
DD
, V
DDQ
V
SS
Address Inputs
Chip Enables
Output Enable
Read/Write S ignal
Clock Enable
Individual Byte Write Selects
Clock
Advance burst address / Load new address
Linear / In terleaved B urst Order
Sleep Mode
Data Input / Output
Core P ower, I/ O Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Static
Asynchronous
Synchronous
Static
Static
5304 tbl 01
SEPTEMBER
2010
1
DSC-5304/07
AS8C803601, AS8C801801, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
™
Commercial
Temperature Range
Pin Definitions
(1)
Symbol
A
0
-A
18
ADV/LD
Pin Function
Address Inputs
Advance / Load
I/O
I
I
Active
N/A
N/A
Description
Synchronous Address inputs. The address register is trig gered by a combination of the
rising edge of CLK, ADV/LD lo w,
CEN
low, and true chip e nables.
ADV/LD is a synchronous input that is used to load the internal registers with new address
and control when it is sampled low at the rising edge of clock with the chip selected. When
ADV/LD is low with the chip deselected, any burst in progress is terminated. When ADV/
LD
is sampled hig h then the internal burst counter is advanced for any burst that was in
progress. The external addresses are ignored when ADV/LD is s ampled high.
R/W signal is a synchronous input that identifies whether the current load cycle initiated is a
Read or Write access to the memory array. The data bus activity for the current cycle takes
place two clock cycles later.
Synchronous Clock Enable Input. When
CEN
is sampled high, all other synchronous
inputs, including clock are ignored and outputs re main unchanged. The effect of
CEN
sampled high on the device outp uts is as if the low to hig h clock transition did not occur.
For normal operation,
CEN
must be s ampled low at rising edge of clock.
Synchro nous byte write enables. Each 9-bit byte has its own active low byte write enable.
On load write cycles (When R/W and ADV/LD are sampled low) the appropriate byte write
signal (BW
1
-BW
4
) must be valid. The byte write signal must also be valid on each cycle of
a burst write. Byte Write signals are ignored when R/W is sampled high. The appropriate
byte(s) of data are written into the device two cycles later.
BW
1
-BW
4
can all be tied low if
always doing write to the entire 36-bit word.
Synchronous active low c hip e nable.
CE
1
an d
CE
2
are used with CE
2
to e nable the
AS8C
803601/ 801801
(CE
1
or
CE
2
sampled high or CE
2
sampled low) and ADV/LD lo w at the
rising edge of clock, initiates a deselect cycle. The ZBT
TM
has a two cycle deselect, i.e.,
the data bus will tri-state two clock cycles after deselect is initiated.
Synchrono us active high c hip e nable. CE
2
is used with
CE
1
and
CE
2
to enable the chip.
CE
2
has inverted po larity but otherwise identical to
CE
1
and
CE
2
.
This i s the c lock input to theAS8C803601/801801. Except for
OE,
all timing references for the
device are made with respect to the rising edge of CLK.
Synchro nous data i nput/output (I/O) p ins. B oth the d ata i nput path and d ata output p ath a re
registered and triggered by the rising edge of CLK.
Burst order selection input. When
LBO
is high the Interleaved burst sequence is selected.
When
LBO
is low the Line ar burst sequence is selected.
LBO
i s a static input and it m ust
not change during device operation.
Asynchronous o utput
e
nable.
OEm
ust b e lo w to read data fromtheAS8C803601/801801.When
OE
is high the I/O pins are in a high-impedance state.
OE
does not need to be actively
controlled for read and write cycles. In no rmal operation,
OE
can be tied low.
Asynchro nous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
AS8C803601/801801
to its lowest p ower consumption level.Data retention is guaranteed in
Sleep Mode.
3.3V core power supply.
3.3V I/O Supply.
Ground.
5304tbl 02
R/W
Read / Write
I
N/A
CEN
Clock Enable
I
LOW
BW
1
-BW
4
Individual B yte
Write E nables
I
LOW
CE
1
,
CE
2
Chip E nables
I
LOW
CE
2
CLK
I/O
0
-I/O
31
I/O
P1
-I/O
P4
LBO
Chip Enable
Clock
Data Inp ut/Output
Linear Burst Order
I
I
I/O
I
HIGH
N/A
N/A
LOW
OE
Output Enable
I
LOW
ZZ
Sleep Mode
I
N/A
V
DD
V
DDQ
V
SS
NOTE:
Power Supply
Power Supply
Ground
N/A
N/A
N/A
N/A
N/A
N/A
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.42
2
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
™
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperatur e Ranges
Functional Block Diagram
LBO
512x18 BIT
MEMORY ARRAY
D
Q
Address
Address A [0:18]
CE1,
CE2,
CE2
R/W
CEN
ADV/LD
BWx
D
Q
Control
Input Register
DI
DO
D
Clk
Q
Control Logic
Mux
Sel
D
Clk
Clock
Output Register
Q
OE
Gate
5304 drw 01
,
Data I/O [0:15],
I/O P[1:2]
6.42
3
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
™
Functional Block Diagram
LBO
Address A [0:18]
CE1,
CE2,
CE2
R/W
CEN
ADV/LD
BWx
D
Clk
Input Register
512x18 BIT
MEMORY ARRAY
D
Q
Address
D
Q
Control
DI
DO
Q
Control Logic
Mux
Sel
D
Clk
Clock
Output Register
Q
OE
Gate
5304 drw 01
,
Data I/O [0:15],
I/O P[1:2]
Recommended DC Operating
Conditions
Symbol
V
DD
V
DDQ
V
SS
V
IH
V
IH
V
IL
Parameter
Core S upply Voltage
I/O S upply Voltage
Supply Voltage
Input High Voltage - Inputs
Input High Voltage - I/O
Input L ow V oltage
Min.
3.135
3.135
0
2.0
2.0
-0.3
(1)
CYC
/2,
Typ.
3.3
3.3
0
____
____
____
Max.
3.465
3.465
0
V
DD
+0.3
V
DDQ
+0.3
0.8
Unit
V
V
V
V
V
V
5304 tbl 04
NOTES:
1. V
IL
(min.) = –1.0V for pulse width less than t
once per cycle.
6.42
4
Recommended Operating
Temperature and Suppl V
y oltage
Grade
Commercial
Industrial
NOTES:
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
™
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperatur e Ranges
Ambient
Temperature
(1)
0° C to +70° C
-40°C to +85°C
V
SS
0V
0V
V
DD
3.3V±5%
3.3V±5%
V
DDQ
3.3V±5%
3.3V±5%
5304 tbl 05
1.
During production testing, the case temperature equals the ambient temperature
.
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/O
P3
I/O
16
I/O
17
V
DDQ
V
SS
I/O
18
I/O
19
I/O
20
I/O
21
V
SS
V
DDQ
I/O
22
I/O
23
V
DD
(1)
V
DD
V
DD
(1)
V
SS
I/O
24
I/O
25
V
DDQ
V
SS
I/O
26
I/O
27
I/O
28
I/O
29
V
SS
V
DDQ
I/O
30
I/O
31
I/O
P4
CE
2
BW
4
BW
3
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
NC
(2)
A
17
A
8
A
9
Pin Configuration - 256K x 36
A
6
A
7
CE
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O
P2
I/O
15
I/O
14
V
DDQ
V
SS
I/O
13
I/O
12
I/O
11
I/O
10
V
SS
V
DDQ
I/O
9
I/O
8
V
SS
V
DD
(1)
V
DD
ZZ
I/O
7
I/O
6
V
DDQ
V
SS
I/O
5
I/O
4
I/O
3
I/O
2
V
SS
V
DDQ
I/O
1
I/O
0
I/O
P1
5304 drw 02
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the input voltage
≥
isVIH.
2. Pin 84 is reserved for a future 16M.
3.
DNU= Do not use. Pins 38, 39, 42 and 43 are reserved for respective JTAG pins: TMS, TDI, TDO and TCK. The
current die revision allows these pins to be left unconnected, tied LOW (V
SS
),
LBO
A
5
A
4
A
3
A
2
A
1
A
0
DNU
(3)
DNU
(3)
V
SS
V
DD
DNU
(3)
DNU
(3)
A
10
A
11
A
12
A
13
A
14
A
15
A
16
,
Top View
100 T
QFP
or tied HIGH (V
DD
).
6.42
5
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