DATASHEET
QUAD PLL FOR DTV
Description
The ICS487-25 generates five high-quality,
high-frequency clock outputs. It is designed to replace
crystals and crystal oscillators in DTV applications.
Using IDT’s patented Phase Locked Loop (PLL)
techniques, the device runs from a lower frequency
crystal or clock input.
Because there is zero ppm frequency synthesis error on
the audio clocks, the audio will remain locked to the
video.
ICS487-25
Features
•
•
•
•
•
•
•
Packaged in 16-pin TSSOP (Pb-free)
Replaces multiple crystals and oscillators
Input crystal or clock frequency of 27 MHz
Zero ppm frequency synthesis error
Duty cycle of 45/55
Operating voltage of 3.3 V
Advanced, low power CMOS process
Block Diagram
VDD
3
2
S1:0
PLL1
ACLK
20M
PLL2
48M
PLL3
33.0M
27 MHz
clock or
crystal
input
X1/ICLK
X2
Crystal
Oscillator/
Clock
Buffer
PLL4
24.576M
External capacitors
may be required.
3
GND
PDTS
(all outputs and PLLs)
IDT™ / ICS™
QUAD PLL FOR DTV
1
ICS487-25
REV B 092109
ICS487-25
QUAD PLL FOR DTV
CLOCK SYNTHESIZER
Pin Assignment
X1/ICLK
S0
S1
48M
VDD
GND
20M
24.576M
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X2
VDD
PDTS
GND
VDD
GND
33.0M
ACLK
ACLK Output Selection Table
S1
0
0
1
1
S0
0
1
0
1
ACLK (MHz)
18.432
16.9344
12.288
18.432
Note: When S1 and S0 are switched, all other output
clocks will remain stable throughout the transition.
16 pin (173 mil) TSSOP
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
X1/ICLK
S0
S1
48M
VDD
GND
20M
24.576M
ACLK
33.0M
GND
VDD
GND
PDTS
VDD
X2
Pin
Type
Input
Input
Input
Output
Power
Power
Output
Output
Output
Output
Power
Power
Power
Input
Power
Input
Pin Description
Crystal connection. Connect to 27 MHz crystal or clock input.
Select pin 0. Determines ACLK output frequency per table above.
Internal pull up resistor.
Select pin 1. Determines ACLK output frequency per table above.
Internal pull up resistor.
48 MHz clcok output. Weak internal pull-down when tri-state.
Connect to +3.3 V.
Connect to ground.
20 MHz clock output. Weak internal pull-down when tri-state.
24.576 MHz clock output. Weak internal pull-down when tri-state.
Audio clock output. Determined by table above. Weak internal
pull-down when tri-state
33.0 MHz clock output. Weak internal pull-down when tri-state.
Connect to ground.
Connect to +3.3 V.
Connect to ground.
Powers down entire chip and tri-states outputs when low. Internal
pull-up resistor.
Connect to +3.3 V.
Connect to 27 MHz crystal or float for clock input.
IDT™ / ICS™
QUAD PLL FOR DTV
2
ICS487-25
REV B 092109
ICS487-25
QUAD PLL FOR DTV
CLOCK SYNTHESIZER
External Components
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
ICS487-25 must be isolated from system power supply
noise to perform optimally.
A decoupling capacitor of 0.01µF must be connected
between each VDD and the PCB ground plane.
-6 pF)*2. In this equation, C
L
= crystal load capacitance
in pF. Example: For a crystal with a 16 pF load
capacitance, each crystal capacitor would be 20 pF
[(16-6) x 2] = 20.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01µF decoupling capacitors should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between the decoupling capacitors and VDD pins. The
PCB trace to VDD pins should be kept as short as
possible, as should the PCB trace to the ground via.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) To minimize EMI, the 33Ω series termination resistor
(if needed) should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed away
from the ICS487-25. This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω
.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors must
be connected from each of the pins X1 and X2 to
ground.
The value (in pF) of these crystal caps should equal (C
L
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS487-25. These ratings,
which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +70° C
IDT™ / ICS™
QUAD PLL FOR DTV
3
ICS487-25
REV B 092109
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