CAV24C128
EEPROM Serial 128-Kb I
2
C
- Automotive Grade 1
The CAV24C128 is a EEPROM Serial 128−Kb I
2
C, internally
organized as 16,384 words of 8 bits each.
It features a 64−byte page write buffer and supports both the
Standard (100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I
2
C
protocol.
Write operations can be inhibited by taking the WP pin High (this
protects the entire memory).
On−Chip ECC (Error Correction Code) makes the device suitable
for high reliability applications.
Features
Description
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TSSOP−8
Y SUFFIX
CASE 948AL
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Automotive Temperature Grade 1 (−40°C to +125°C)
Supports Standard, Fast and Fast−Plus I
2
C Protocol
2.5 V to 5.5 V Supply Voltage Range
64−Byte Page Write Buffer
Hardware Write Protection for Entire Memory
Schmitt Triggers and Noise Suppression Filters on I
2
C Bus Inputs
(SCL and SDA)
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
8−lead SOIC and TSSOP Packages
This Device is Pb−Free, Halogen Free/BFR Free and RoHS
Compliant*
V
CC
SOIC−8
W SUFFIX
CASE 751BD
PIN CONFIGURATION
A
0
A
1
A
2
V
SS
SOIC (W), TSSOP (Y)
For the location of Pin 1, please consult the
corresponding package drawing.
1
V
CC
WP
SCL
SDA
PIN FUNCTION
SCL
CAV24C128
SDA
Pin Name
A
0
, A
1
, A
2
A
2
, A
1
, A
0
WP
SDA
SCL
WP
V
CC
V
SS
V
SS
Function
Device Address Inputs
Serial Data Input/Output
Serial Clock Input
Write Protect Input
Power Supply
Ground
Figure 1. Functional Symbol
* For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
©
Semiconductor Components Industries, LLC, 2012
May, 2018
−
Rev. 1
1
Publication Order Number:
CAV24C128/D
CAV24C128
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Storage Temperature
Voltage on Any Pin with Respect to Ground (Note 1)
Rating
−65
to +150
−0.5
to +6.5
Units
°C
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than
−0.5
V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than
−1.5
V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS
(Note 2)
Symbol
N
END
(Notes 3, 4)
T
DR
Endurance
Data Retention
Parameter
Min
1,000,000
100
Units
Program / Erase Cycles
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V
CC
= 5 V, 25°C
4. This device uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when a single byte
has to be written, 4 bytes (including the ECC bits) are re−programmed. It is recommended to write by multiple of 4 bytes in order to benefit
from the maximum number of write cycles.
Table 3. D.C. OPERATING CHARACTERISTICS
(V
CC
= 2.5 V to 5.5 V, T
A
=
−40°C
to +125°C, unless otherwise specified.)
Symbol
I
CCR
I
CCW
I
SB
I
L
V
IL
V
IH
V
OL
Parameter
Read Current
Write Current
Standby Current
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
I
OL
= 3.0 mA
All I/O Pins at GND or V
CC
Pin at GND or V
CC
T
A
=
−40°C
to +125°C
T
A
=
−40°C
to +125°C
−0.5
0.7 V
CC
Test Conditions
Read, f
SCL
= 400 kHz/1 MHz
Min
Max
1
3
5
2
0.3 V
CC
V
CC
+ 0.5
0.4
Units
mA
mA
mA
mA
V
V
V
Table 4. PIN IMPEDANCE CHARACTERISTICS
(V
CC
= 2.5 V to 5.5 V, T
A
=
−40°C
to +125°C, unless otherwise specified.)
Symbol
C
IN
(Note 5)
C
IN
(Note 5)
I
WP
, I
A
(Note 6)
Parameter
SDA I/O Pin Capacitance
Input Capacitance (other pins)
WP Input Current, Address Input
Current (A
0
, A
1
, A
2
)
V
IN
= 0 V
V
IN
= 0 V
V
IN
< V
IH
, V
CC
= 5.5 V
V
IN
< V
IH
, V
CC
= 3.3 V
V
IN
> V
IH
Conditions
Max
8
6
75
50
2
Units
pF
pF
mA
5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
6. When not driven, the WP, A
0
, A
1
, A
2
pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V
CC
), the strong pull−down reverts to a weak current source.
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CAV24C128
Table 5. A.C. CHARACTERISTICS
(V
CC
= 2.5 V to 5.5 V, T
A
=
−40°C
to +125°C) (Note 7)
Standard
Symbol
F
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
(Note 8)
t
F
(Note 8)
t
SU:STO
t
BUF
t
AA
t
DH
T
i
(Note 8)
t
SU:WP
t
HD:WP
t
WR
t
PU
(Notes 8, 9)
7.
8.
9.
Parameter
Clock Frequency
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between
STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
Noise Pulse Filtered at SCL
and SDA Inputs
WP Setup Time
WP Hold Time
Write Cycle Time
Power-up to Ready Mode
0
2.5
5
1
100
100
0
2.5
5
1
0.1
4
4.7
3.5
100
100
0
1
5
1
4
4.7
4
4.7
0
250
1,000
300
0.6
1.3
0.9
50
50
Min
Max
100
0.6
1.3
0.6
0.6
0
100
300
300
0.25
0.5
0.40
Min
Fast
Max
400
0.25
0.45
0.40
0.25
0
50
100
100
Fast−Plus
Min
Max
1,000
Units
kHz
ms
ms
ms
ms
ms
ns
ns
ns
ms
ms
ms
ns
ns
ms
ms
ms
ms
Test conditions according to “A.C. Test Conditions” table.
Tested initially and after a design or process change that affects this parameter.
t
PU
is the delay between the time V
CC
is stable and the device is ready to accept commands.
Table 6. A.C. TEST CONDITIONS
Input Levels
Input Rise and Fall Times
Input Reference Levels
Output Reference Levels
Output Load
0.2 x V
CC
to 0.8 x V
CC
v
50 ns
0.3 x V
CC
, 0.7 x V
CC
0.5 x V
CC
Current Source: I
OL
= 3 mA; C
L
= 100 pF
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CAV24C128
Power−On Reset (POR)
The CAV24C128 incorporates Power−On Reset (POR)
circuitry which protects the device against powering up in
the wrong state.
The CAV24C128 will power up into Standby mode after
V
CC
exceeds the POR trigger level and will power down into
Reset mode when V
CC
drops below the POR trigger level.
This bi−directional POR feature protects the device against
‘brown−out’ failure following a temporary loss of power.
Pin Description
SCL:
The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA:
The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this pin
is open drain. Data is acquired on the positive edge, and is
delivered on the negative edge of SCL.
A
0
, A
1
and A
2
: The Address pins accept the device address.
When not driven, these pins are pulled LOW internally.
WP:
The Write Protect input pin inhibits all write
operations, when pulled HIGH. When not driven, this pin is
pulled LOW internally.
Functional Description
The CAV24C128 supports the Inter−Integrated Circuit
(I
2
C) Bus data transmission protocol, which defines a device
that sends data to the bus as a transmitter and a device
receiving data as a receiver. Data flow is controlled by a
Master device, which generates the serial clock and all
START and STOP conditions. The CAV24C128 acts as a
Slave device. Master and Slave alternate as either
transmitter or receiver. Up to 8 devices may be connected to
the bus as determined by the device address inputs A
0
, A
1
,
and A
2
.
I
2
C Bus Protocol
The I
2
C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the V
CC
supply via pull−up
resistors. Master and Slave devices connect to the 2−wire
bus via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while SCL
is HIGH will be interpreted as a START or STOP condition
(Figure 2). The START condition precedes all commands. It
consists of a HIGH to LOW transition on SDA while SCL
is HIGH. The START acts as a ‘wake−up’ call to all
receivers. Absent a START, a Slave will not respond to
commands. The STOP condition completes all commands.
It consists of a LOW to HIGH transition on SDA while SCL
is HIGH.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8−bit
serial Slave address. The first 4 bits of the Slave address are
set to 1010, for normal Read/Write operations (Figure 3).
The next 3 bits, A
2
, A
1
and A
0
, select one of 8 possible Slave
devices and must match the state of the external address pins.
The last bit, R/W, specifies whether a Read (1) or Write (0)
operation is to be performed.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA line
during the 9
th
clock cycle (Figure 4). The Slave will also
acknowledge all address bytes and every data byte presented
in Write mode. In Read mode the Slave shifts out a data byte,
and then releases the SDA line during the 9
th
clock cycle. As
long as the Master acknowledges the data, the Slave will
continue transmitting. The Master terminates the session by
not acknowledging the last data byte (NoACK) and by
issuing a STOP condition. Bus timing is illustrated in
Figure 5.
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CAV24C128
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2. START/STOP Conditions
DEVICE ADDRESS
1
0
1
0
A
2
A
1
A
0
R/W
Figure 3. Slave Address Bits
BUS RELEASE DELAY (TRANSMITTER)
SCL FROM
MASTER
DATA OUTPUT
FROM TRANSMITTER
1
8
9
BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT
FROM RECEIVER
START
ACK DELAY (≤ t
AA
)
ACK SETUP (≥ t
SU:DAT
)
Figure 4. Acknowledge Timing
t
F
t
LOW
SCL
t
SU:STA
SDA IN
t
AA
SDA OUT
t
HD:STA
t
HIGH
t
LOW
t
R
t
HD:DAT
t
SU:DAT
t
SU:STO
t
DH
t
BUF
Figure 5. Bus Timing
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