SERCON816
SERCOS INTERFACE CONTROLLER
s
s
s
s
s
s
s
s
s
s
s
s
Single-chip controller for SERCOS interface
Real time communication for industrial control
systems
8/16-bit bus interface, Intel and Motorola control
signals
Dual port RAM with 2048 word *16-bit
Data communications via optical fiber rings, RS
485 rings and RS 485 busses
Maximum transmission rate of 16 Mbaud with
internal clock recovery
Internal repeater for ring connections
Full duplex operation
Modulation of power of optical transmitter diode
Automatic transmission of synchronous and
data telegrams in the communication cycle
Flexible RAM configuration, communication
data stored in RAM (single or double buffer) or
transfer via DMA
Synchronization by external signal
PQFP100
ORDERING NUMBERS: SERC816
SERC816/TR
s
s
s
s
s
Timing control signals
Automatic service channel transmission
Watchdog to monitor software and external
synchronization signals
Compatible mode to SERCON410B SERCOS
interface controller
100-pin plastic flat-pack casing
Figure 1. SERCON816 Block Diagram
WRN
D[15:0]
A[15:0]
ALEL
ALEH
BUS N
Y
MCS
N0/1
P N0
CS
BHEN
PCS
1
R
DN
ADMUX
BUS
MODE[1:0]
BUS
WIDT
H
BY E
T DIR
bus interfac e
inter-
rupt
c loc k
reset
INT
0/1
S
CLK
S
CLK
O2/4
MCLK
RS N
T
DMAR
EQR/T
DMAACKNR/T
DMA
watc h-
dog
telegram-
proc essing
timing-
c ontrol
WDOGN
CY
C_CLK
CON_CLK
DIV_CLK
S
BAUD
S
BAUD16
T
M0/1
serial
interfac e
L_E
RRN
R
ECACT
N
IDLE
R
xC
R
xD
T
xC
T
xD[6:1]
optical transm itter/
receiver or
RS
-485 bus drive
January 2003
1/23
SERCON816
TABLE OF CONTENTS
GENERAL DESCRIPTION.................................................................................................................3
Pin Description ...................................................................................................................................5
Electrical (DC and AC) Characteristics ..............................................................................................7
3.1 Absolute Maximum Ratings .....................................................................................................7
3.2 Recommended Operating Conditions ......................................................................................8
3.3 ELECTRICAL CHARACTERISTCS ........................................................................................8
3.4 Power Dissipation ....................................................................................................................9
3.4.1 Power Dissipation Considerations....................................................................................9
3.5 AC Electrical Characteristics..................................................................................................10
3.5.1 Clock Input MCLK...........................................................................................................10
3.5.2 Clock Input SCLK ...........................................................................................................11
3.5.3 Address Latch.................................................................................................................11
3.5.4 Read Access of Control Registers..................................................................................12
3.5.5 Read Access of Dual Port RAM .....................................................................................13
3.5.6 Write Access to Control Registers..................................................................................14
3.5.7 Write Access to DUAL Port RAM ...................................................................................15
Control Registers and RAM Data Structures....................................................................................16
4.1 Control Register Addresses ...................................................................................................16
4.2 Data Structures within the RAM .............................................................................................16
4.2.1 Telegram Headers..........................................................................................................16
4.2.2 Data Containers..............................................................................................................17
4.2.3 End Marker .....................................................................................................................18
4.2.4 Service Containers .........................................................................................................18
Additional Specifications, Tools and Support ...................................................................................21
5.1 Additional Specifications ........................................................................................................21
5.2 Hardware and Software Components ....................................................................................21
5.3 Tools ......................................................................................................................................21
Package Mechanical Data:
SERCON816 100 Pin Plastic Quad Flat Pack Package (PQFP100) ...............................................22
1
2
3
4
5
6
2/23
SERCON816
1
GENERAL DESCRIPTION
The SERCOS interface controller SERCON816 is an integrated circuit for SERCOS interface communication
systems. The SERCOS interface is a digital interface for communication between systems which have to ex-
change information cyclically at short, fixed intervals (62,5 s to 65 ms). It is appropriate for the synchronous
operation of distributed control or test equipment (e.g. connection between drives and numeric control).
A SERCOS interface communication system consists of one master and several slaves. These units are
connected by a fiber optical ring. This ring starts and ends at the master. The slaves regenerate and repeat
their received data or send their own telegrams. By this method the telegrams sent by the master are re-
ceived by all slaves while the master receives data telegrams from the slaves. The optical fiber assures a
reliable high-speed data transmission with excellent noise immunity.
The SERCOS interface controller contains all the hardware-related functions of the SERCOS interface and
considerably reduces the hardware costs and the computing time requirements of the microprocessor. It is
the direct link between the electro-optical receiver and transmitter and the microprocessor that executes the
control algorithms. The SERCON816 can be used both for SERCOS interface masters and slaves.
The circuit contains the following functions (Fig. 1):
– Interface to the microprocessor with a data bus width of 8 or 16 bits and with control lines according to
Intel or Motorola standards.
– A serial interface for making a direct connection with the optical receiver and transmitter of the fiber optic ring
or with drivers to an electric ring or bus. Data and clock regeneration, the repeater for ring topologies and the
serial transmitter and receiver are integrated. The signals are monitored and test signals generated. The se-
rial interface operates up to 16 Mbaud without external circuitry.
– A dual port RAM (2048 * 16 bit) for control and communication data. The organization of the memory is flexible.
– Telegram processing for automatic transmission and monitoring of synchronous and data telegrams. Only
transmission data which is intended for the particular interface user is processed. The transmitted data is ei-
ther stored in the internal RAM (single or double buffer) or transferred via direct memory access (DMA). The
transmission of service channel information over several communication cycles is executed automatically.
In addition to the SERCOS interface the SERCON816 can also be used for other real-time communica-
tions tasks. As an alternative to the fiber optical ring also bus topologies with RS-485 signals are supported
(Fig. 4). The SERCON816 is therefore suitable for a wide range of applications.
Remark: The SERCON816 is based on the former SERCON410B SERCOS interface controller.
Figure 2. SERCON816 Pin Configuration
80 D12
D13
D14
D15
VDD
75 BHEN
A0
A1
A2
A3
70 VSS
A4
A5
A6
A7
65 VDD
A8
A9
A10
A11
60 VSS
A12
A13
A14
A15
55 VDD
ALEL
ALEH
WRN
51 RDN
VSS 81
D11
D10
D9
D8 85
VDD
D7
D6
D5
D4 90
VSS
D3
D2
D1
D0 95
ADMUX
BUSMODE0
BUSMODE1
BUSWIDTH
BYTDIR 100
SERCON816
50 VSS
PCS1
PCSN0
MCSN1
MCSN0
45 BUSYN
INT0
INT1
VSS
DMAACKTN
40 DMAACKRN
DMAREQT
DMAREQR
VDD
DIV_CLK
35 CON_CLK
CYC_CLK
VSS
L_ERRN
31 TM1
VDD 1
SCLK
VSS
MCLK
SCLK04 5
SCLK02
TEST
VDD
NDTRO
RSTN 10
OUTZ
RxC
TxC
RxD
VSS 15
TxD1
TxD2
TxD3
VDD
TxD4 20
TxD5
TxD6
VSS
WDOGN
IDLE 25
RECACTN
VDD
SBAUD16
SBAUD
TM0 30
3/23
SERCON816
Figure 3. SERCON816 with Ring Connection (SERCOS interface)
µP
bus interfac e
S
ERCON816
m aster
fibre
optical
ring
RxD
T
xD
RxD
T
xD
RxD
T
xD
S
ERCON816
S CON816
ER
S RCON816
E
bus interfac e
bus interfac e
bus interfac e
µP
µP
µP
slave
1
slave
2
slave
n
Figure 4. SERCON816 with RS-485 bus connection
µP
bus interfac e
SR
E CON816
m a ster
IDLE
IDLE
SR
E CON816
IDLE
SR
E CON816
IDLE
SR
E CON816
b us
interfa c e
b us
interfa ce
bus
interfac e
µP
sla ve
1
µP
S R ING.CDR
E CR
µP
2
slave
n
slave
4/23
SERCON816
2
PIN DESCRIPTION
Table 1. SERCON816 I/O Port Function Summary
Signal(s)
D15-0
Pin(s)
77-80,
82-85,
87-90,
92-95
54, 53
IO
I/O
Function
Data bus: for 8-bit-wide bus interfaces, data is wri
tt
en to and read via D7-0, for
16-bit-wide bus interfaces via D15-0. When ADMUX is 1, the address which is
stored in the address latch with ALEL and ALEH is input via D15-0.
Address latch enable, low and high, active high: they are only used when
ADMUX is 1. When ALEL/ALEH is 1, the signals go from the data bus to the
address bus, when ALEL/ALEH = 0, they store the address. When ADMUX is
0, ALEL/ALEH have to be connected to VDD.
Read: for the Intel bus interface, data is read when RDN is 0. For the Motorola
bus interface, data is read or written to when RDN is 0 (BUSMODE1 = 0) or
RDN is 1 (BUSMODE1 = 1).
Write: for the Intel bus interface, data is written to when WRN is 0. For the
Motorola bus interace, WRN selects read (WRN = 1) and write (WRN = 0)
operations of the data bus.
Byte high enable, active low: in the 16-bit bus mode, data is transferred via
D15-8 when BHEN is 0.
Memory chip select, active low: to access the internal RAM MCSN0 and
MCSN1 must be 0.
Periphery chip select, active low (PCSN0) and active high (PCS1): to access
the control registers PCSN0 must equal 0 and PCS1 must equal 1.
RAM busy, active low: becomes active if an access to an address of the dual
port RAM is performed simultaneously to an access to the same memory
location by the internal telegram processing.
DMA request receive, active high: becomes active if data from the receive
FIFO can be read. At the beginning of the read operation of the last word of
the receive FIFO, DMAREQR becomes inactive.
DMA acknowledge receive, active low: when DMAACKRN is 0, the receive
FIFO is read, independent of the levels on A6-1 and the chip select signals.
DMA request transmit, active high: becomes active when data can be written
to the transmit FIFO. DMAREQT becomes inactive again at the beginning of
the last write access to the transmit FIFO.
DMA acknowledge transmit, active low: when DMAACKTN is 0, the transmit
FIFO is written to when there is a bus write access independent of the levels
on A6-1 and the chip select signals.
Address data bus: when ADMUX is 0 A15-0 are the address inputs, when
ADMUX is 1 A15-0 are the outputs of the address latch.
Bus mode: BUSMODE0 = 0 turns on the Intel bus interface (RDN = read,
WRN = write), BUSMODE0 = 1 selects the Motorola interface (RDN = data
strobe, WRN = read/write). BUSMODE1 selects the 0-active data strobe
(BUSMODE1 = 0) or the 1-active data strobe (BUSMODE1 = 1).
Bus width: selects the 8-bit- (0) or the 16-bit-wide interface (1).
Byte address sequence: when BYTEDIR is 0, A0 = 0 addresses the lower 8
bits of a word (low byte first), when BYTEDIR is 1, the upper 8 bits of a word
are addressed (high byte first).
Interrupts, active low or active high. Interrupt sources and signal polarity are
programmable.
Baud rate and SERCON410B compatible mode: SBAUD and SBAUD16
selects the baud rate for the serial interface. If SBAUD16 is ‘1’ the
SERCON410B compatible mode is selected.
Baud rate. Can be overwritten by the microprocessor.
ALEL, ALEH
I
RDN
51
I
WRN
52
I
BHEN
MCSN0,
MCSN1
PCSN0,
PCS1
BUSYN
75
46,47
48,49
45
I
I
I
O
DMAREQR
38
O
DMAACKRN
DMAREQT
40
39
I
O
DMAACKTN
41
I
ADMUX
BUSMODE0,
BUSMODE1
96
97,98
I
I
BUSWIDTH
BYTEDIR
99
100
I
I
INT0, INT1
SBAUD16
44,43
28
O
I
SBAUD
29
I
5/23
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