CTSLVEL16VR
MLP8, MLP16
PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable
FEATURES
Minimizes External Components
Selectable Enable Polarity and
Threshold (CMOS or PECL)
High Bandwidth for
1GHz
Similar Operation as CTS100EL16
-147 dBc/Hz Typical Noise Floor
BLOCK DIAGRAM
DESCRIPTION
The CTSLVEL16VR is a specialized oscillator gain stage with a high gain output buffer including an enable
function. The Q
HG
/Q
HG
outputs have voltage gain several times greater than the Q/Q outputs. It provides a
¯
¯
selectable Q
HG
/Q
HG
enable that allows continuous oscillator operation via the Q/Q outputs.
¯
¯
The CTSLVEL16VR provides adjustable internal pull-down current sources for the Q/Q outputs and
¯
optional 10mA current sources for the Q
HG
/Q
HG
outputs. Internal input biasing further reduces the number
¯
of needed external components.
ENGINEERING NOTES
Functionality of MLP16 Package (CTSLVEL16VRNLG)
The CTSLVEL16VRNLG provides a selectable Q
HG
/Q
HG
enable that allows continuous oscillator operation
¯
via the Q/Q outputs. Table 1 shows the operating modes. Leaving EN-SEL open (NC) selects PECL/ECL
¯
operation for the EN pad/pin. In this mode the Q
HG
/Q
HG
outputs are enabled when EN is left open (NC) or
¯
set to a PECL/ECL low.
Connecting EN-SEL to V
CC
, V
EE
or V
BB
selects CMOS operation for the EN pad/pin. When EN-SEL is tied
to V
EE
, the Q
HG
/Q
HG
outputs are disabled when EN is left open (NC). When EN-SEL is tied to V
CC
or V
BB
,
¯
the Q
HG
/Q
HG
outputs are enabled when EN is left open. This default logic condition can be overridden by a
¯
20k resistor connected to the opposite supply.
The CTSLVEL16VRNLG also provides a V
BB
and 470 internal bias resistors from D to V
BB
and D to V
BB
.
¯
The V
BB
pin supports 1.5mA sink/source current. V
BB
should be bypassed to ground or V
CC
with a 0.01
F
capacitor.
Outputs Q/Q each have a selectable on-chip pull-down current source. See Table 2 for the supported
¯
values. External resistors may also be used to increase pull-down current to a maximum total of 25mA for
the Q/Q outputs.
¯
¯
Each of the Q
HG
/Q
HG
outputs has an optional on-chip pull-down current source of 10mA. When pad/pin
V
EEP
is left open (NC), the output current sources are disabled and the Q
HG
/Q
HG
operate as standard
¯
PECL/ECL. When V
EEP
is connected to V
EE
, the current sources are activated. The Q
HG
/Q
HG
pull-down
¯
current can be decreased by using a resistor between V
EEP
and V
EE
.
North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors
Specifications are subject to change without notice.
1
RevB0114
CTSLVEL16VR
MLP8, MLP16
PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable
EN-SEL
NC
V
EE1
V
CC
or V
BB1,2
1
2
Table 1 - Enable Truth Table
EN
Q/Q
¯
PECL Low, V
EE
or NC
PECL High or V
CC
CMOS Low, V
EE
or NC
CMOS High or V
CC
CMOS Low or V
EE
CMOS High, V
CC
or NC
Data
Data
Data
Data
Data
Data
Q
HG
Data
Low
Low
Data
Low
Data
Q
HG
¯
Data
High
High
Data
High
Data
EN-SEL connections must be
≤1Ω.
Date codes prior to 0428 do not support this operating mode.
Table 2 - Current Source Truth Table
CS-SEL
Q
Q
¯
NC
V
EE1
V
CC1
1
4mA typ
8mA typ
0
4mA typ
8mA typ
4mA typ
Connection must be less than 1Ω.
Figure below illustrates the timing sequences for the CTSLVEL16VRNLG in the MLP 16 package. It is shown
here with the enable operating in active Low mode with a PECL threshold. This mode is determined by
leaving the EN-SEL open (NC). An active High enable with a CMOS/TTL threshold is also an option.
CTSLVEL16VRNLG Timing Diagram
North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors
Specifications are subject to change without notice.
2
RevB0114
CTSLVEL16VR
MLP8, MLP16
PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable
Functionality MLP8 Package (CTSLVEL16VRNNG)
A CMOS enable input (EN) allows continuous oscillator operation. When the EN input is HIGH or left open
(NC), the Q and Q
HG
/Q
HG
outputs follow the data input. When EN is LOW, the Q
HG
output is forced high and
¯
¯
the Q
HG
output is forced low while Q continues to follow the data input. The Q output has an internal 4 mA
¯
¯
¯
current source to V
EE
, in most cases eliminating the need for an external pull-down resistor.
The CTSLVEL16VRNNG also provides biasing. Data input D is tied to the VBB pin through a 470 internal
bias resistor while the inverting input D is connected directly to V
BB
. The V
BB
pin supports 1.5mA sink/source
¯
current. V
BB
should be bypassed to ground with a 0.01
F
capacitor.
CTSLVEL16VRNNG Timing
1000
900
800
700
600
500
400
300
200
100
0
0
500
1000
1500
2000
2500
FREQUENCY (MHz)
3000
3500
4000
North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors
Specifications are subject to change without notice.
3
RevB0114
V
OUTpp
(mV)
CTSLVEL16VR
MLP8, MLP16
PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable
AC Coupling Capacitor
C2
R1
See table
EL16VO
Front End
3.3 or 5 V
CMOS
D
R2
470
Ω
D
V
BB
C1
0.01
μF
Application Circuit for CMOS Inputs
Recommended Component Values for CMOS Single Ended Inputs
R1
1
Value
Input Type
AC Coupled (C2 in
DC Coupled (C2
circuit)
shorted)
3.3V CMOS
1.1 kΩ
2.0 kΩ
5.0V CMOS
1.6 kΩ
3.3 kΩ
1
R1 should be chosen so that the input swing on the D input with respect to D
¯
is in the range of ±80 to ±1000 mV, per the AC Characteristics table and the D
input is < ±750 mV with respect to V
BB
.
North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors
Specifications are subject to change without notice.
4
RevB0114
CTSLVEL16VR
MLP8, MLP16
PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable
S11 50Ω external AC, 4 & 8mA internal DC load
S12 50Ω external AC, 4 & 8mA internal DC load
North Americas: +1-800-757-6686 • International: +1-508-435-6831 • Asia: +65-655-17551 • www.ctscorp.com/semiconductors
Specifications are subject to change without notice.
5
RevB0114
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