Low Skew, Dual, Differential-to-LVDS
Fanout Buffer
General Description
The ICS854S036 is a low skew, high performance
Dual Differential-to-LVDS Fanout Buffer. One of the
HiPerClockS™
two fanout buffers has 3 LVDS outputs, the other has 6
LVDS outputs. The PCLKx, nPCLKx pairs can accept
most standard differential input levels. The
ICS854S036 is characterized to operate from a 3.3V power supply.
Guaranteed output and bank skew characteristics make the
ICS854S036 ideal for those clock distribution applications
demanding well defined performance and repeatability.
ICS854S036
DATA SHEET
Features
•
•
•
•
•
•
•
•
•
•
•
•
Two independent differential LVDS output buffers, buffer A with
three outputs, buffer B with 6 outputs
Two differential clock input pairs
PCLKx, nPCLKx pairs can accept the following differential input
levels: LVPECL, LVDS, CML, SSTL
Output frequency: 2GHz
Translates any single ended input signal to LVDS levels with
resistor bias on nPCLKx input
Output skew: 100ps (maximum)
Bank skew: 20ps (maximum)
Propagation delay: 550ps (maximum)
Additive phase jitter, RMS: 0.06ps (typical)
Full 3.3V power supply
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
ICS
Block Diagram
QA0
nQA0
PCLKA
Pulldown
nPCLKA
Pullup
QA1
nQA1
QA2
nQA2
QB0
nQB0
PCLKB
Pulldown
nPCLKB
Pullup
QB1
nQB1
QB2
nQB2
QB3
nQB3
QB4
nQB4
QB5
nQB5
Pin Assignment
nQA0
nQA1
nQA2
32 31 30 29 28 27 26 25
GND
PCLKA
nPCLKA
GND
V
DD
PCLKB
nPCLKB
V
DD
1
2
3
4
5
6
7
8
9
GND
GND
QA0
QA1
QA2
V
DD
24
23
22
21
20
19
18
17
10 11 12 13 14 15 16
nQB3
nQB5
nQB4
QB5
QB4
QB3
V
DD
V
DD
QB0
nQB0
QB1
nQB1
QB2
nQB2
GND
ICS854S036
32-Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
ICS854S036 REVISION A NOVEMBER 16, 2009
1
©2009 Integrated Device Technology, Inc.
ICS854S036 Data Sheet
LOW SKEW, DUAL, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Table 1. Pin Descriptions
Number
1, 4, 9, 17, 25
2
3
5, 8, 16, 24, 32
6
7
10, 11
12, 13
14, 15
18, 19
20, 21
22, 23
26, 27
28, 29
30, 31
Name
GND
PCLKA
nPCLKA
V
DD
PCLKB
nPCLKB
nQB5, QB5
nQB4, QB4
nQB3, QB3
nQB2, QB2
nQB1, QB1
nQB0, QB0
nQA2, QA2
nQA1, QA1
nQA0, QA0
Power
Input
Input
Power
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Pulldown
Pullup
Pulldown
Pullup
Type
Description
Power supply ground.
Non-inverting differential clock input.
Inverting differential clock input.
Power supply pins.
Non-inverting differential clock input.
Inverting differential clock input.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
Ω
k
Ω
Table 3. Clock Input Function Table
Inputs
PCLKA, PCLKB
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nPCLKA, nPCLKB
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Outputs
QA[0:2], QB[0:5]
LOW
HIGH
LOW
HIGH
HIGH
LOW
nQA[0:2], nQB[0:5]
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single-ended to Differential
Single-ended to Differential
Single-ended to Differential
Single-ended to Differential
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
Inverting
NOTE 1: Refer to the Application Information Section,
Wiring the Differential Input to Accept Single-ended Levels.
ICS854S036 REVISION A NOVEMBER 16, 2009
2
©2009 Integrated Device Technology, Inc.
ICS854S036 Data Sheet
LOW SKEW, DUAL, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuos Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
42.7°C/W (0 mps)
-65°C to 150°C
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
210
Units
V
mA
Table 4B. LVPECL Differential DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
I
IH
Parameter
PCLKA, PCLKB
Input High Current
nPCLKA, nPCLKB
PCLKA, PCLKB
I
IL
V
PP
V
CMR
Input Low Current
nPCLKA, nPCLKB
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1, 2
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-10
-150
0.25
GND + 1.25
1.0
V
DD
Minimum
Typical
Maximum
150
10
Units
µA
µA
µA
µA
V
V
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
Table 4C. LVDS DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
OD
∆V
OD
V
OS
∆V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.125
Test Conditions
Minimum
247
Typical
Maximum
454
50
1.375
50
Units
mV
mV
V
mV
ICS854S036 REVISION A NOVEMBER 16, 2009
3
©2009 Integrated Device Technology, Inc.
ICS854S036 Data Sheet
LOW SKEW, DUAL, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Table 5. AC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
f
OUT
t
PD
tsk(o)
tsk(b)
tjit
t
R
/ t
F
odc
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
Bank Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Output Rise/Fall Time
Output Duty Cycle
100MHz, Integration Range:
12kHz – 20MHz
20% to 80%
100
48
0.06
250
52
300
Test Conditions
Minimum
Typical
Maximum
2
550
100
20
Units
GHz
ps
ps
ps
ps
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured from the output differential cross points.
NOTE 3: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
ICS854S036 REVISION A NOVEMBER 16, 2009
4
©2009 Integrated Device Technology, Inc.
ICS854S036 Data Sheet
LOW SKEW, DUAL, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the
dBc Phase
Noise.
This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 100MHz
12kHz to 20MHz = 0.06ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
IFR2042 10kHz - 5.4GHz Low Noise Signal Generator as external
input to a Hewlett Packard 8133A 3GHz Pulse Generator.
ICS854S036 REVISION A NOVEMBER 16, 2009
5
©2009 Integrated Device Technology, Inc.
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