Data Sheet
FEATURES
Outstanding gain linearity
Ultrahigh gain, 5000 V/mV min
Low V
OS
over temperature, 55 μV max
TCV
OS
, 0.3 μV/°C max
High PSRR, 3 μV/V max
Low power consumption, 60 mW max
Available in die form
Next Generation OP07 Ultralow
Offset Voltage Operational Amplifier
OP77
PIN CONNECTIONS
V
OS
TRIM
1
–IN
2
+IN
3
TOP VIEW
V–
4
(Not to Scale)
OP77
8
7
6
5
V
OS
TRIM
V+
OUT
00320-001
NC
NC = NO CONNECT
Figure 1. 8-Pin Hermetic
CERDIP_Q-8 (Z Suffix)
V
OS
TRIM
V
OS
TRIM
1
8
V+
7
OP77
–IN
2
6
OUT
3
5
4
+IN
NC
4V– (CASE)
00320-002
TOP VIEW
(Not to Scale)
NC = NO CONNECT
Figure 2. TO-99
(J Suffix)
GENERAL DESCRIPTION
The
OP77
has outstanding gain of 10,000,000 or more that is
maintained over the full 10 V output range. This gain-linearity
eliminates incorrectable system nonlinearities common in
previous monolithic op amps and provides superior performance
in high closed-loop gain applications. Low initial V
OS
drift and
rapid stabilization time, combined with only 50 mW of power
consumption, are significant improvements over previous
designs. These characteristics, plus the TCV
OS
of 0.3 μV/°C
maximum and the low V
OS
of 25 μV maximum, eliminates
the need for V
OS
adjustment and increases system accuracy over
temperature.
A PSRR of 3 μV/V (110 dB) and CMRR of 1.0 μV/V maximum
virtually eliminate errors caused by power supply drifts and
common-mode signals. This combination of outstanding
characteristics makes the
OP77
ideally suited for high resolution
instrumentation and other tight error budget systems.
Rev. G
Document Feedback
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2002–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
OP77
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Connections ............................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Specifications ............................................................... 3
Wafer Test Limits .......................................................................... 4
Typical Electrical Characteristics ............................................... 5
Absolute Maximum Ratings............................................................ 6
Data Sheet
Thermal Resistance .......................................................................6
ESD Caution...................................................................................6
Typical Performance Characteristics ..............................................7
Test Circuits ..................................................................................... 10
Applications..................................................................................... 11
Precision Current Sinks ............................................................. 12
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 16
REVISION HISTORY
10/15—Rev. F to Rev. G
Changes to Features Section and General Description Section..... 1
Changes to Note 1, Ordering Guide.................................................. 16
3/15—Rev. E to Rev. F
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 16
4/10—Rev. D to Rev. E
Removed Figure 33 and Two Subsequent Paragraphs ............... 12
6/09—Rev. C to Rev. D
Changes to Figure 1 and Figure 2 ................................................... 1
Changes to Table 1 ............................................................................ 3
Removed Endnote 1 and Endnote 2 in Table 3 ............................ 4
Changes to Figure 16 ........................................................................ 9
Changes to Figure 31 and Figure 32 ............................................. 12
Changes to Figure 38 ...................................................................... 14
Moved Figure 39 ............................................................................. 14
10/02—Rev. B to Rev. C
Edits to Specifications ...................................................................... 2
Figure 2 Caption Changed ............................................................ 10
Figure 3 Caption Changed ............................................................ 10
Edits to Figure 10 ............................................................................ 11
Updated Outline Dimensions ....................................................... 15
2/02—Rev. A to Rev. B
Remove 8-Lead SO PIN Connection Diagrams ........................... 1
Changes to Absolute Maximum Rating......................................... 2
Remove OP77B column from Specifications ................................ 2
Remove OP77B column from Electrical Characteristics ........ 3, 5
Remove OP77G column from Wafer Test Limits......................... 6
Remove OP77G column from Typical Electrical Characteristics .... 6
Rev. G | Page 2 of 16
Data Sheet
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
@ V
S
= ±15 V, T
A
= 25°C, unless otherwise noted.
Table 1.
Parameter
INPUT OFFSET VOLTAGE
LONG-TERM STABILITY
1
INPUT OFFSET CURRENT
INPUT BIAS CURRENT
INPUT NOISE VOLTAGE
2
INPUT NOISE VOLTAGE DENSITY
Symbol
V
OS
V
OS
/time
I
OS
I
B
e
np-p
e
n
Conditions
Min
OP77E
Typ
10
0.3
0.3
+1.2
0.35
10.3
10.0
9.6
14
0.32
0.14
0.12
45
200
±14
0.1
0.7
12,000
±14.0
±13.0
±12.5
0.3
0.6
60
50
3.5
±3
Max
25
1.5
+2.0
0.6
18.0
13.0
11.0
30
0.80
0.23
0.17
Min
OP77F
Typ
20
0.4
0.3
+1.2
0.38
10.5
10.2
9.8
15
0.35
0.15
0.13
45
200
±14
0.1
0.7
6000
±14.0
±13.0
±12.5
0.3
0.6
60
50
3.5
±3
Max
60
2.8
+2.8
0.65
20.0
13.5
11.5
35
0.90
0.27
0.18
OP77
−0.2
0.1 Hz to 10 Hz
f
O
= 10 Hz
f
O
= 100 Hz
2
f
O
= 1000 Hz
0.1 Hz to 10 Hz
f
O
= 10 Hz
f
O
= 100 Hz
2
f
O
= 1000 Hz
26
±13
V
CM
= ±13 V
V
S
= ±3 V to ±18 V
R
L
≥ 2 kΩ
V
O
= ±10 V
R
L
≥ 10 kΩ
R
L
≥ 2 kΩ
R
L
≥ 1 kΩ
R
L
≥ 2 kΩ
A
VCL
+ 1
V
S
= ±15 V, no load
V
S
= ±3 V, no load
Rp = 20 kn
−0.2
Unit
μV
μV/Mo
nA
nA
μV
p-p
nV/√Hz
INPUT NOISE CURRENT
2
INPUT NOISE CURRENT DENSITY
i
np-p
i
n
pA
p-p
pA√Hz
INPUT RESISTANCE
Differential Mode
3
Common Mode
INPUT VOLTAGE RANGE
COMMON-MODE REJECTION RATIO
POWER SUPPLY REJECTION RATIO
LARGE-SIGNAL VOLTAGE GAIN
OUTPUT VOLTAGE SWING
R
IN
R
INCM
IVR
CMRR
PSRR
A
VO
V
O
18.5
±13
1.0
3.0
2000
±13.5
±12.5
±12.0
0.1
0.4
60
4.5
1.6
3.0
5000
±13.5
±12.5
±12.0
0.1
0.4
MΩ
GΩ
V
μV/V
μV/V
V/mV
V
SLEW RATE
2
CLOSED-LOOP BANDWIDTH
2
OPEN-LOOP OUTPUT RESISTANCE
POWER CONSUMPTION
OFFSET ADJUSTMENT RANGE
1
SR
BW
R
O
P
d
60
4.5
V/μs
MHz
Ω
mW
mV
Long-term input offset voltage stability refers to the averaged trend line of V
OS
vs. time over extended periods after the first 30 days of operation. Excluding the initial
hour of operation, changes in V
OS
during the first 30 operating days are typically 2.5 μV.
2
Sample tested.
3
Guaranteed by design.
Rev. G | Page 3 of 16
OP77
@ V
S
= ±15 V, −25°C ≤ T
A
≤ +85°C for
OP77FJ
and
OP77E/OP77F,
unless otherwise noted.
Table 2.
Parameter
INPUT OFFSET VOLTAGE
AVERAGE INPUT OFFSET VOLTAGE DRIFT
1
INPUT OFFSET CURRENT
AVERAGE INPUT OFFSET CURRENT DRIFT
2
INPUT BIAS CURRENT
AVERAGE INPUT BIAS CURRENT DRIFT
2
INPUT VOLTAGE RANGE
COMMON-MODE REJECTION RATIO
POWER SUPPLY REJECTION RATIO
LARGE-SIGNAL VOLTAGE GAIN
OUTPUT VOLTAGE SWING
POWER CONSUMPTION
1
2
Data Sheet
Symbol
V
OS
TCV
OS
I
OS
TCI
OS
I
B
TCI
B
IVR
CMRR
PSRR
A
VO
V
O
P
d
Conditions
V
CM
= ±13 V
V
S
= ±3 V to ±18 V
R
L
≥ 2 kΩ
V
O
= ±10 V
R
L
≥ 2 kΩ
V
S
= ±15 V, no load
OP77E
Min
Typ
10
0.1
0.5
1.5
−0.2
+2.4
8
±13.0 ±13.5
0.1
1.0
2000
6000
±12
±13.0
60
Max
45
0.3
2.2
4.0
+4.0
40
1.0
3.0
OP77F
Min
Typ
20
0.2
0.5
1.5
−0.2
+2.4
15
±13.0 ±13.5
0.1
1.0
1000
4000
±12
±13.0
60
Max
100
0.6
4.5
85
+6.0
60
3.0
5.0
Unit
µV
µV/°C
nA
pA/°C
nA
pA/°C
V
pV/V
µV/V
V/mV
V
mW
75
75
OP77E:
TCV
OS
is 100% tested on J and Z packages.
Guaranteed by end-point limits.
WAFER TEST LIMITS
@ V
S
= ±15 V, T
A
= 25°C, for
OP77NBC
devices, unless otherwise noted.
Table 3.
Parameter
INPUT OFFSET VOLTAGE
INPUT OFFSET CURRENT
INPUT BIAS CURRENT
INPUT RESISTANCE
Differential Mode
INPUT VOLTAGE RANGE
COMMON-MODE REJECTION RATIO
POWER SUPPLY REJECTION RATIO
OUTPUT VOLTAGE SWING
Symbol
V
OS
I
OS
I
B
R
IN
IVR
CMRR
PSRR
V
O
Conditions
OP77NBC
Limit
40
2.0
±2
26
±13
1
3
±13.5
±12.5
±12.0
2000
±30
60
Unit
µV max
nA max
nA max
MΩ min
V min
µV/V max
µV/V max
V min
LARGE-SIGNAL VOLTAGE GAIN
DIFFERENTIAL INPUT VOLTAGE
POWER CONSUMPTION
A
VO
V
CM
= ±13 V
V
S
= ±3 V to ±18 V
R
L
= 10 kΩ
R
L
= 2 kΩ
R
L
= 1 kΩ
R
L
= 2 kΩ
V
O
= ±10 V
V
O
= 0 V
V/mV min
V max
mW max
P
d
Rev. G | Page 4 of 16
Data Sheet
TYPICAL ELECTRICAL CHARACTERISTICS
@ V
S
= ±15 V, T
A
= 25°C, unless otherwise noted.
Table 4.
Parameter
AVERAGE INPUT OFFSET VOLTAGE DRIFT
NULLED INPUT OFFSET VOLTAGE DRIFT
AVERAGE INPUT OFFSET CURRENT DRIFT
SLEW RATE
BANDWIDTH
Symbol
TCV
OS
TCV
OSn
TCI
OS
SR
BW
Conditions
R
S
= 50 Ω
R
S
= 50 Ω, R
P
= 20 kΩ
R
L
≥ 2 kΩ
A
VCL
+ 1
OP77NBC
Limit
0.1
0.1
0.5
0.3
0.6
OP77
Unit
µV/°C
µV/°C
pA/°C
V/µs
MHz
Rev. G | Page 5 of 16