AS4C64M32MD1
Revision History AS4C64M32MD1 - 90-ball FBGA PACKAGE
Revision
Rev 1.0
Details
Preliminary datasheet
Date
September 2014
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice
Confidential
-1-
Rev.1.0
Sep. 2014
AS4C64M32MD1
64M x 32 bit MOBILE DDR Synchronous DRAM (SDRAM)
Confidential
Feature
4 banks x 16M x 32 organization
- Two Die-stacked 4 banks x 16M x 16
-
Data Mask for Write Control (DM)
-
Four Banks controlled by BA0 & BA1
-
Programmable CAS Latency: 2, 3
-
Programmable Wrap Sequence: Sequential
or Interleave
-
Programmable Burst Length:
2, 4, 8, for Sequential Type
-
2, 4, 8, for Interleave Type
-
Automatic and Controlled Precharge Command
-
Power Down Mode
-
Auto Refresh and Self Refresh
-
Refresh Interval: 8192 cycles/64ms
-
Available in 90-ball BGA
-
Double Data Rate (DDR)
-
Bidirectional Data Strobe (DQS) for input
and output data, active on both edges
-
Differential clock inputs CLK and /CLK
-
Power Supply 1.7V - 1.95V
-
Drive Strength (DS) Option:Full, 1/2, 1/4, 1/8
-
Auto Temperature-Compensated Self Refresh
(Auto TCSR)
-
Partial-Array Self Refresh (PASR) Option: Full,
1/2, 1/4, 1/8, 1/16
-
Deep Power Down (DPD) mode
-
Operating Temperature Range
- Commercial -25°C to 85°C
-
Industrial
-40°C to 85°C
All parts are ROHS Compliant
-
Advanced (Rev. 1.0, Sep. /2014)
Description
The AS4C64M32MD1 is a four bank mobile
DDR DRAM organized as 4 banks x 16M x 32. It
achieves high speed data transfer rates by
employing a chip architecture that pre-fetches
multiple bits and then synchronizes the output data
to a system clock.
All of the controls, address, circuits are
synchronized with the positive edge of an
externally supplied clock. I/O transactions are
possible on both edges of DQS.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at a higher rate than is possible with
standard DRAMs. A sequential and gapless data
rate is possible depending on burst length, CAS
latency and speed grade of the device.
Additionally, the device supports low power
saving features like PASR, Auto-TCSR, DPD as
well as options for different drive strength. It’s
ideally suitable for mobile application.
Table 1. Speed Grade Information
Speed Grade – Data rate Clock Frequency
400Mbps (max)
200 MHz (max)
CAS Latency
3
t
RCD
(ns)
15
t
RP
(ns)
15
Table 2 – Ordering Information for ROHS Compliant Products
Product part No
AS4C64M32MD1-5BCN
AS4C64M32MD1-5BIN
Org
64M x 32
64M x 32
Temperature
Package
Commercial -
25°C
to
85°C
90-ball
FBGA
(Extended)
Industrial -40°C to 85°C
90-ball
FBGA
Confidential
-2-
Rev.1.0
Sep. 2014
AS4C64M32MD1
Block Diagram
Column Addresses
A0 - A9, AP, BA0, BA1
Row Addresses
A0 - A13, BA0, BA1
Column address
counter
Column address
buffer
Row address
buffer
Refresh Counter
Row decoder
Memory array
Column decoder
Sense amplifier & I(O) bus
Row decoder
Memory array
Bank B
Row decoder
Memory array
Bank C
Row decoder
Memory array
Bank D
Bank A
Column decoder
Sense amplifier & I(O) bus
Column decoder
Sense amplifier & I(O) bus
Column decoder
Sense amplifier & I(O) bus
16384 x 1024
x32 bits
16384 x 1024
x32 bits
16384 x 1024
x32 bits
16384 x 1024
x32 bits
Input buffer
Output buffer
Control logic & timing generator
DQ
0
-DQ
31
CLK, CLK
Strobe
Gen.
Data Strobe
DM0 ~ DM3
CKE
RAS
CLK
CLK
CAS
WE
CS
DQS0~DQS3
Confidential
-3-
Rev.1.0
Sep. 2014
AS4C64M32MD1
90 BALL BGA
CONFIGURATION
Top View
9
A
B
C
D
E
F
G
H
J
K
8
7
6
5
Pin Names
CLK, CLK
CKE
CS
RAS
CAS
WE
DQS0, DQS1
DQS2, DQS3
A
0
–A
13
Differential Clock Input
Clock Enable
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Data Strobe (Bidirectional)
Address Inputs
BA0, BA1
DQ
0
–DQ
31
DM0, DM1
DM2, DM3
V
DD
V
SS
V
DDQ
V
SSQ
Bank Select
Data Input/Output
Data Mask
Power (1.7V - 1.95V)
Ground
Power for I/O’s (1.7V - 1.95V)
Ground for I/O’s
Confidential
-4-
Rev.1.0
Sep. 2014
AS4C64M32MD1
Signal Pin Description
Pin
CLK
CLK
CKE
Type
Input
Signal
Pulse
Polarity
Positive
Edge
Function
The system clock input. All inputs except DQs and DMs are sampled on the rising
edge of CLK.
Input
Level
Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby
initiates either the Power Down mode, Suspend mode, or the Self Refresh mode.
Active Low CS enables the command decoder when low and disables the command decoder
when high. When the command decoder is disabled, new commands are ignored but
previous operations continue.
Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
command to be executed by the SDRAM.
—
During a Bank Activate command cycle, A0-A13 defines the row address (RA0-RA13)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-
CA9) when sampled at the rising clock edge.
In addition to the column address, A10 is used to invoke autoprecharge operation at
the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and
BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10(=AP) is used in conjunction with BA0 and
BA1 to control which bank(s) to precharge. If A10 is high, all four banks will be pre-
charged simultaneously regardless of state of BA0 and BA1.
CS
Input
Pulse
RAS, CAS
WE
A0 - A13
Input
Pulse
Input
Level
DQx
Input/
Output
Input
Level
Data Input/Output pins operate in the same manner as conventional DRAMs.
BA0,
BA1
DQS0,DQS1
DQS2,DQS3
Level
—
Selects which bank is to be active.
Input/
Output
Level
—
Data Strobes : Output with read data, input with write data. Edge-aligned with read
data, centered in write data. it is used to fetch write data. For the x32, DQS0 corre-
sponds to the data on DQ0-DQ7; DQS1 corresponds to the data on DQ8-DQ15,
DQS2 corresponds to the data on DQ16-DQ23, DQS3 corresponds to the data on
DQ24-DQ31
DM0,DM1
DM2,DM3
Input
Pulse
Active High Input Data Mask : DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH along with that input data during a WRITE access. DM is
sampled on both edges of DQS. DM pins include dummy loading inter-nally, to match
the DQ and DQS loading. For the x32, DM0 corresponds to the data on DQ0-DQ7;
DM1 corresponds to the data on DQ8-DQ15, DM2 corresponds to the data on DQ16-
DQ23, DM3 corresponds to the data on DQ24-DQ31
Power and ground for the input buffers and the core logic.
VDD, VSS
VDDQ,VSSQ
Supply
Supply
—
—
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
Confidential
-5-
Rev.1.0
Sep. 2014
FPGA/CPLD
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