• Phase-locked loop (PLL) clock distribution for double
data rate synchronous DRAM applications
• Distributes one clock input to ten differential outputs
• External feedback pin (FBIN) is used to synchronize the
outputs to the clock input
• Conforms to the DDRI specification
• Spread Aware for electromagnetic interference (EMI)
reduction
• 48-pin SSOP package
Description
This PLL clock buffer is designed for 2.5-V
DD
and 2.5-AV
DD
operation and differential outputs levels.
This device is a zero delay buffer that distributes a clock input
(CLKIN) to ten differential pairs of clock outputs (YT[0:9],
YC[0:9]) and one feedback clock output (FBOUT). The clock
outputs are individually controlled by the serial inputs SCLK
and SDATA.
The two-line serial bus can set each output clock pair (YT[0:9],
YC[0:9]) to the Hi-Z state. When AV
DD
is grounded, the PLL is
turned off and bypassed for the test purposes.
The PLL in this device uses the input clock (CLKIN) and the
feedback clock (FBIN) to provide high-performance, low-skew,
low-jitter output differential clocks.
Block Diagram
10
Pin Configuration
YT0
YC0
YT1
YC1
YT2
YC2
SCLK
SDATA
YT4
YC4
YT5
YC5
YT6
YC6
CLKIN
PLL
FBIN
YT7
YC7
YT8
YC8
YT9
YC9
CY28351
Serial
Interface
Logic
YT3
YC3
AVDD
FBOUT
VSS
YC0
YT0
VDDQ
YT1
YC1
VSS
VSS
YC2
YT2
VDD
SCLK
CLKIN
NC
VDDI
AVDD
AVSS
VSS
YC3
YT3
VDDQ
YT4
YC4
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VSS
YC5
YT5
VDDQ
YT6
YC6
VSS
VSS
YC7
YT7
VDDQ
SDATA
NC
FBIN
VDDQ
FBOUT
NC
VSS
YC8
YT8
VDDQ
YT9
YC9
VSS
Cypress Semiconductor Corporation
Document #: 38-07370 Rev. *B
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised May 23, 2003
CY28351
Pin Description
[1]
Pin Number
13
35
3, 5, 10, 20, 22
46, 44, 39, 29, 27
2, 6, 9, 19, 23
47, 43, 40, 30, 26
33
Pin Name
CLKIN
FBIN
YT(0:9)
YC(0:9)
FBOUT
I/O
I
I
O
O
O
Clock Input.
Feedback Clock Input.
Connect to FBOUT for
accessing the PLL.
Clock Outputs.
Clock Outputs.
Feedback Clock Output.
Connect to FBIN for
normal operation. A bypass delay capacitor at this
output will control Input Reference/Output Clocks
phase relationships.
Output
Pin Description
Electrical Characteristics
Input
Input
Differential Outputs
12
37
SCLK
SDATA
I
I/O
Serial Clock Input.
Clocks data at SDATA into the Data Input for the two-line serial
internal register.
bus
Serial Data Input.
Input data is clocked to the
Data Input and Output for the
internal register to enable/disable individual outputs. two-line serial bus
This provides flexibility in power management.
2.5V Power Supply for Logic.
2.5V Power Supply for Output Clock Buffers.
2.5V Power Supply for PLL.
Common Ground.
2.5V Nominal
2.5V Nominal
2.5V Nominal
0.0V Ground
0.0V Analog Ground
11
4, 21, 28, 34, 38,
45
16
15
1, 7, 8, 18, 24, 25,
31, 41, 42, 48
17
14, 32,36
VDD
VDDQ
AVDD
VDDI
VSS
AVSS
NC
–
2.5V Power Supply for Two-line Serial Interface.
2.5V Nominal
Analog Ground.
Not Connected.
Zero Delay Buffer
When used as a zero delay buffer, the CY28351 will likely be
in a nested clock tree application. For these applications the
CY28351 offers a clock input as a PLL reference. The
CY28351 then can lock onto the reference and translate with
near zero delay to low skew outputs. For normal operation, the
external feedback input, FBIN, is connected to the feedback
output, FBOUT. By connecting the feedback output to the
feedback input the propagation delay through the device is
eliminated. The PLL works to align the output edge with the
input reference edge thus producing a near zero delay. The
reference frequency affects the static phase offset of the PLL
and thus the relative delay between the inputs and outputs.
When V
DDA
is strapped LOW, the PLL is turned off and
bypassed for test purposes.
Function Table
Input
V
DDA
GND
GND
2.5V
2.5V
2.5V
CLKIN
L
H
L
H
< 20 MHz
YT(0:9)
[2]
L
H
L
H
Hi-Z
Outputs
YC(0:9)
[2]
H
L
H
L
Hi-Z
FBOUT
L
H
L
H
Hi-Z
PLL
BYPASSED/OFF
BYPASSED/OFF
On
On
Off
Notes:
1. A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins
their high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
2. Each output pair can be three-stated via the two-line serial interface.
Document #: 38-07370 Rev. *B
Page 2 of 8
CY28351
Power Management
The individual output enable/disable control of the CY28351
allows the user to implement unique power management
schemes into the design. Outputs are three-stated when
disabled through the two-line interface as individual bits are
set LOW in Byte0 and Byte1 registers. The feedback output
(FBOUT) cannot be disabled via two line serial bus. The
enabling and disabling of individual outputs is done in such a
manner as to eliminate the possibility of partial “runt” clocks.
Storage Temperature: .................................–65°C to +150°C
Operating Temperature: .................................... 0°C to +70°C
Maximum Power Supply: ................................................3.5V
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, V
IN
and V
OUT
should be constrained to
the range:
V
SS
< (V
IN
or V
OUT
) < V
DD
.
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
or V
DD
).
DC Parameters
V
DD
= V
DDA
= V
DDQ
= V
DDI
= 2.5V + 5%, T
A
= 0°C to +70°C
[4]
Parameter
Description
V
IL
Input Low Voltage
V
IH
V
IL
V
IH
I
IN
I
OL
I
OH
V
OL
V
OH
V
OUT
V
OC
I
OZ
I
DDQ
ID
STAT
I
DD
C
IN
Parameter
fCLK
tDC
tLOCK
Tr/Tf
tpZL, tpZH
tpLZ, tpHZ
tCCJ
tjit(h-per)
tPLH
tPHL
tSKEW
tPHASE
tPHASEJ
Input High Voltage
Input Voltage Low
Input Voltage High
Input Current
Output Low Current
Output High Current
Output Low Voltage
Output High Voltage
Output Voltage Swing
[5]
Output Crossing Voltage
[6]
High-Impedance Output Current
Dynamic Supply
Static Supply Current
Current
[7]
V
O
= GND or V
O
= V
DDQ
All V
DDQ
and V
DDI
, F
O
= 170 MHz
V
DDA only
Condition
SDATA , SCLK
SDATA , SCLK
CLKIN, FBIN
CLKIN, FBIN
V
IN
= 0V or V
IN
= V
DDQ
, CLKT, FBIN
V
DDQ
= 2.375V, V
OUT
= 1.2V
V
DDQ
= 2.375V, V
OUT
= 1V
V
DDQ
= 2.375V, I
OL
= 12 mA
V
DDQ
= 2.375V, I
OH
= –12 mA
Min.
2.2
0.4
2.1
–10
26
–18
1.7
V
DDQ
– 0.4
(V
DDQ
/2) V
DDQ
/2 (V
DDQ
/2)
– 0.2
+ 0.2
–10
10
235
9
4
300
1
12
6
1.1
35
–32
0.6
10
Typ.
Max.
1.0
Unit
V
V
V
V
µA
mA
mA
V
V
V
V
µA
mA
mA
mA
pF
PLL Supply Current
Input Pin Capacitance
AC Parameters
V
DD
= V
DDQ
= 2.5V ± 5%, T
A
= 0°C to + 70°C
[8,9]
Description
Operating Clock Frequency
Input Clock Duty Cycle
Maximum PLL lock Time
Output Clocks Slew Rate
Output Enable Time (all
Output Disable Time (all outputs)
[10]
Cycle to Cycle Jitter
[12]
Half-period jitter
[12]
LOW-to-HIGH Propagation Delay, CLKIN to YT
HIGH-to-LOW Propagation Delay, CLKIN to YT
Any Output to Any Output Skew
[11]
Phase Error
[11]
Phase Error Jitter
f > 66 MHz
f > 66 MHz
f > 66 MHz
–100
–100
1.5
1.5
–150
–50
3.5
3.5
outputs)
[10]
20% to 80% of VOD
Condition
Min. Typ. Max. Unit
60
40
1
3
3
100
100
6
6
100
150
50
200 MHz
60
%
100
µs
2.5 V/ns
ns
ns
ps
ps
ns
ns
ps
ps
ps
Notes:
3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4. unused inputs must be held HIGH or LOW to prevent them from floating.
5. For load conditions, see
Figure 7.
6. The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120Ω resistor. See
Figure 7.
7. All outputs switching loaded with 16 pF in 60Ω environment. See
Figure 7.
8. Parameters are guaranteed by design and characterization. Not 100% tested in production
9. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 33.3 kHz with a down
spread of –0.5%.
10. Refers to transition of non-inverting output.
11. All differential input and output terminals are terminated with 120Ω/16 pF, as shown in
Figure 7.
12. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other.
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