Low Skew, 1-to-5, Differential-To-
3.3V LVPECL Fanout Buffer
General Description
The ICS85304I-01 is a low skew, high performance 1-to-5
Differential-to-3.3V LVPECL fanout buffer. The ICS85304I-01 has
two selectable clock inputs. The CLKx, nCLKx pairs can accept most
standard differential input levels. The clock enable is internally
synchronized to eliminate runt clock pulses on the outputs during
asynchronous assertion/ deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make the
ICS85304I-01 ideal for those applications demanding well defined
performance and repeatability.
ICS85304I-01
DATASHEET
Features
•
•
•
•
•
•
•
•
•
•
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Five 3.3V differential LVPECL output pairs
Selectable differential CLKx, nCLKx input pairs
CLKx, nCLKx input pairs can accept the following differential
levels: LVDS, LVPECL, LVHSTL and HCSL levels
Maximum output frequency: 650MHz
Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on nCLKx inputs
Output skew: 60ps (maximum)
Part-to-part skew: 300ps (maximum)
Propagation delay: 2.1ns (maximum)
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) package
Block Diagram
CLK_EN
Pullup
D
Q
CLK0
Pulldown
nCLK0
Pullup
CLK1
Pulldown
nCLK1
Pullup
CLK_SEL
Pulldown
LE
0
0
1
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Pin Assignment
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
CLK_EN
V
CC
nCLK1
CLK1
V
EE
nCLK0
CLK0
CLK_SEL
V
CC
ICS85304I-01
20-Lead TSSOP
6.5mm x 4.4mm x 0.925mm
package body
G Package
Top View
ICS85304AGI-01 REVISION A FEBRUARY 4, 2013
1
©2013 Integrated Device Technology, Inc.
ICS85304I-01 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER
Pin Description and Pin Characteristics Tables
Table 1. Pin Descriptions
Number
1, 2
3, 4
5, 6
7, 8
9,
10
11, 18, 20
12
13
14
15
16
17
19
Name
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
V
CC
CLK_SEL
CLK0
nCLK0
V
EE
CLK1
nCLK1
CLK_EN
Output
Output
Output
Output
Output
Power
Input
Input
Input
Power
Input
Input
Input
Pulldown
Pullup
Pullup
Pulldown
Pulldown
Pullup
Type
Description
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Positive supply pins.
Clock select input. When HIGH, selects CLK1, nCLK1 inputs. When LOW,
selects CLK0, nCLK0 inputs. LVTTL/LVCMOS interface levels.
Non-inverting differential clock input.
Inverting differential clock input.
Negative supply pin.
Non-inverting differential clock input.
Inverting differential clock input.
Synchronizing clock enable. When HIGH, clock outputs follow clock input.
When LOW, Qx outputs are forced LOW, nQx outputs are forced HIGH.
LVTTL/LVCMOS interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
ICS85304AGI-01 REVISION A FEBRUARY 4, 2013
2
©2013 Integrated Device Technology, Inc.
ICS85304I-01 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER
Function Tables
Table 3A. Control Input Function Table
Inputs
CLK_EN
0
0
1
1
CLK_SEL
0
1
0
1
Selected Source
CLK0, nCLK0
CLK1, nCLK1
CLK0, nCLK0
CLK1, nCLK1
Q[0:4]
Disabled; LOW
Disabled; LOW
Enabled
Enabled
Outputs
nQ[0:4]
Disabled; HIGH
Disabled; HIGH
Enabled
Enabled
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLKx, nCLKx inputs as described in Table 3B.
Disabled
nCLK[0:1]
CLK[0:1]
Enabled
CLK_EN
nQ[0:4]
Q[0:4]
Figure 1.
CLK_EN
Timing Diagram
Table 3B. Clock Input Function Table
Inputs
CLK0 or CLK1
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nCLK0 or nCLK1
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Q[0:4]
LOW
HIGH
LOW
HIGH
HIGH
LOW
Outputs
nQ[0:4]
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
Inverting
NOTE 1: Please refer to the Application Information section,
Wiring the Differential Input to Accept Single-Ended Levels.
ICS85304AGI-01 REVISION A FEBRUARY 4, 2013
3
©2013 Integrated Device Technology, Inc.
ICS85304I-01 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
91.1°C/W
(0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
=0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
Parameter
Core Supply Voltage
Power Supply Current
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
55
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input High
Current
Input Low
Current
CLK_EN
CLK_SEL
CLK_EN
CLK_SEL
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-150
-5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
5
150
Units
V
V
µA
µA
µA
µA
I
IL
Table 4C. Differential DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
Parameter
Input High
Current
Input Low
Current
nCLK0, nCLK1
CLK0, CLK1
nCLK0, nCLK1
CLK0, CLK1
Test Conditions
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-150
-5
0.15
V
EE
+ 0.5
1.3
V
CC
– 0.85
Minimum
Typical
Maximum
5
150
Units
µA
µA
µA
µA
V
V
I
IL
V
PP
V
CMR
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage;
NOTE 1, 2
NOTE 1: V
IL
should not be less than -0.3V
NOTE 2: Common mode input voltage is defined as V
IH
.
ICS85304AGI-01 REVISION A FEBRUARY 4, 2013
4
©2013 Integrated Device Technology, Inc.
ICS85304I-01 Data Sheet
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO- 3.3V LVPECL FANOUT BUFFER
Table 4D. LVPECL DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
=0V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Current; NOTE 1
Output Low Current; NOTE 1
Peak-to-Peak Output Voltage
Swing
Test Conditions
Minimum
V
CC
– 1.4
V
CC
– 2.1
0.6
Typical
Maximum
V
CC
– 0.9
V
CC
– 1.7
1.0
Units
µA
µA
V
NOTE 1: Outputs terminated with 50
to V
CC
– 2V.
AC Electrical Characteristics
Table 5. AC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
=0V, T
A
= -40°C to 85°C
Parameter
f
OUT
t
PD
tsk(o)
tsk(pp)
t
R
/ t
F
odc
Symbol
Maximum Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 3
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
300
45
ƒ
650MHz
1.0
Test Conditions
Minimum
Typical
Maximum
650
2.1
60
300
700
55
Units
MHz
ns
ps
ps
ps
%
NOTE: The device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating
temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied
individually under normal operating conditions and not valid simultaneously.
NOTE: All parameters measured at 500MHz unless noted otherwise
NOTE 1: Measured from the differential input crossing point to the differential output crosspoint.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
crosspoint.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoint.
ICS85304AGI-01 REVISION A FEBRUARY 4, 2013
5
©2013 Integrated Device Technology, Inc.
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