Differential-to-LVCMOS/LVTTL Fanout
Buffer w/Divider and Glitchless Switch
General Description
The ICS870S208 is a low skew, eight output LVCMOS / LVTTL
Fanout Buffer with selectable divider. The ICS870S208 has two
selectable inputs that accept a variety of differential input types. The
device provides the capability to suppress any glitch at the outputs of
the device during an input clock switch to enhance clock redundancy
in fault tolerant applications. The low impedance LVCMOS outputs
are designed to drive 50series or parallel terminated transmission
lines. The effective fanout can be increased from 8 to 16 by utilizing
the ability of the outputs to drive two series terminated lines. The
divide select inputs, DIV_SELA and DIV_SELB, control the output
frequency of each bank. The output banks can be independently
selected for ÷1 or ÷2 operation. The output enable pins assigned to
each output, support enabling and disabling of each output
individually.
The ICS870S208 is characterized at full 3.3V and 2.5V, and mixed
3.3V/2.5V output operating supply modes. Guaranteed output and
part-to-part skew characteristics make the ICS870S208 ideal for
high performance, single ended applications.
ICS870S208
DATASHEET
Features
•
•
•
•
•
•
•
•
•
Eight LVCMOS/LVTTL outputs, (2 banks of 4 outputs)
Each output has individual synchronous output enable
Two selectable differential CLKx, nCLKx inputs
Dual differential input pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL
Maximum output frequency: 250MHz
Selectable
1
or
2
operation
Glitchless output behavior during input switch
Output skew: 120ps (maximum), 3.3V
Bank skew: 65ps (maximum), 3.3V
Supply modes:
Core/Output
3.3V/3.3V
2.5V/2.5V
3.3V/2.5V
0°C to 70°C ambient operating temperature
Lead-free (RoHS 6) packaging
•
•
Block Diagram
DIV_SELA
Pulldown
CLK0
Pulldown
nCLK0
Pullup
CLK1
Pulldown
nCLK1
Pullup
CLK_SEL
Pulldown
QA0
OE_A0
Pin Assignment
V
DDOA
V
DDOB
GND
QA3
GND
QB2
QA2
QB3
32 31 30 29 28 27 26 25
0
÷1
0
QA1
OE_A1
DIV_SELB
CLK0
nCLK0
V
DD
CLK_SEL
CLK1
nCLK1
DIV_SELA
1
2
3
4
5
6
7
8
9
GND
24
23
22
21
20
19
18
17
10 11 12 13 14 15 16
QB0
V
DDOA
V
DDOB
GND
QA0
QA1
QB1
OE_B3
OE_B2
OE_B1
OE_B0
OE_A3
OE_A2
OE_A1
OE_A0
÷2
1
1
QA2
OE_A2
QA3
OE_A3
QB0
OE_B0
0
QB1
OE_B1
1
DIV_SELB
Pulldown
QB2
OE_B2
QB3
OE_B3
ICS870S208
32-Lead VFQFN
5mm x 5mm x 0.9mm package body
3.15mm x 3.15mm EPad Size
K Package
Top View
ICS870S208BKLF REVISION A APRIL 3, 2013
1
©2013 Integrated Device Technology, Inc.
ICS870S208 Data Sheet
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER W/DIVIDER AND GLITCHLESS SWITCH
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1
2
3
4
5
6
7
8
9, 16, 25, 32
10, 11,
30, 31
12, 29
13, 28
14, 15
26, 27
17
18
19
20
21
22
23
24
Name
DIV_SELB
CLK0
nCLK0
V
DD
CLK_SEL
CLK1
nCLK1
DIV_SELA
GND
QA0, QA1,
QA3, QA2
V
DDOA
V
DDOB
QB0, QB1,
QB3, QB2
OE_A0
OE_A1
OE_A2
OE_A3
OE_B0
OE_B1
OE_B2
OE_B3
Input
Input
Input
Power
Input
Input
Input
Input
Power
Output
Power
Power
Output
Input
Input
Input
Input
Input
Input
Input
Input
Pullup
Pullup
Pullup
Pullup
Pullup
Pullup
Pullup
Pullup
Pulldown
Pulldown
Pullup
Pulldown
Type
Pulldown
Pulldown
Pullup
Description
Controls frequency division for Bank B outputs. LVCMOS / LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input.
Power supply pin.
Clock select input. When HIGH, selects CLK1, nCLK1 inputs, When LOW, selects
CLK0, nCLK0 inputs. LVCMOS / LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input.
Controls frequency division for Bank A outputs. LVCMOS / LVTTL interface levels.
Power supply ground.
Single-ended Bank A clock outputs. LVCMOS / LVTTL interface levels.
Output supply pins for Bank A outputs.
Output supply pins for Bank B outputs.
Single-ended Bank B clock outputs. LVCMOS / LVTTL interface levels.
Output enable for QA0 output. Active HIGH. If OE pin is LOW, outputs will drive in
high-impedance. See Table 3. LVCMOS / LVTTL interface levels.
Output enable for QA1 output. Active HIGH. If OE pin is LOW, outputs will drive in
high-impedance. See Table 3. LVCMOS / LVTTL interface levels.
Output enable for QA2 output. Active HIGH. If OE pin is LOW, outputs will drive in
high-impedance. See Table 3. LVCMOS / LVTTL interface levels.
Output enable for QA3 output. Active HIGH. If OE pin is LOW, outputs will drive in
high-impedance. See Table 3. LVCMOS / LVTTL interface levels.
Output enable for QB0 output. Active HIGH. If OE pin is LOW, outputs will drive in
high-impedance. See Table 3. LVCMOS / LVTTL interface levels.
Output enable for QB1 output. Active HIGH. If OE pin is LOW, outputs will drive in
high-impedance. See Table 3. LVCMOS / LVTTL interface levels.
Output enable for QB2 output. Active HIGH. If OE pin is LOW, outputs will drive in
high-impedance. See Table 3. LVCMOS / LVTTL interface levels.
Output enable for QB3 output. Active HIGH. If OE pin is LOW, outputs will drive in
high-impedance. See Table 3. LVCMOS / LVTTL interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
ICS870S208BKLF REVISION A APRIL 3, 2013
2
©2013 Integrated Device Technology, Inc.
ICS870S208 Data Sheet
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER W/DIVIDER AND GLITCHLESS SWITCH
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
V
DD
= V
DDOA, B
= 3.465V
Power Dissipation
Capacitance (per output)
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
V
DD
= V
DDOA, B
= 2.625V
V
DD
= 3.465V, V
DDOA, B
= 2.625V
Test Conditions
Minimum
Typical
2
8
7
7
50
50
15
Maximum
Units
pF
pF
pF
pF
k
k
Function Tables
Table 3. Output Enable Function Table
Control Inputs
OE_x [0:3]
0
1 (default)
NOTE: Where x = A or B.
Outputs
QA[0:3], QB[0:3]
High-Impedance
Active
ICS870S208BKLF REVISION A APRIL 3, 2013
3
©2013 Integrated Device Technology, Inc.
ICS870S208 Data Sheet
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER W/DIVIDER AND GLITCHLESS SWITCH
Function Description
Two Valid Clocks
The ICS87S0208 has a glitch free input mux that is controlled by the
CLK_SEL pin. It is designed to switch between 2 input clocks
whether running or not.
In the case where both clocks are running,
when CLK_SEL changes, the output clocks go low after one cycle of
the output clock (nominally). The outputs then stay low for one cycle
of the new input clock (nominally) and then begin to follow the new
input clock. This is shown in
Figure 1A.
CLK0
CLK1
CLK_SEL
Output
Figure 1A. CLK_SEL Timing Diagram
When DIV_SEL changes, the part waits for the output to complete
the cycle of the selected divider then changes seamlessly to the new
divider.
CLK ÷ 1
CLK ÷ 2
DIV_SEL
Output
Figure 1B. DIV_SELx Timing Diagram
When an output enable pin is pulled low, the part waits for the output
to complete its period, then transitions to an High-Impedance state.
When output enable is asserted, the output transitions from a
High-Impedance to a low state to ensure a clean rising edge of the
first output clock.
CLK1
OE
Output
Figure 1C. OEx Timing Diagram
ICS870S208BKLF REVISION A APRIL 3, 2013
4
©2013 Integrated Device Technology, Inc.
ICS870S208 Data Sheet
DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER W/DIVIDER AND GLITCHLESS SWITCH
Bad Input Clock
An internal timer monitors the state of both input clocks. If a clock is
stopped (stuck high or low for over approximately 200ns), its internal
input bad flag is set and the part will perform as depicted in the
following diagrams. If the clock is restored, the internal input bad
detector waits for 4 full clock periods before clearing the input bad
flag and returning to normal operation.
If the selected input clock goes bad (stuck high or low for over
approximately 200ns), an internal input bad flag is set. When the
input bad flag is set, the output goes low until the next valid clock
event. If the selected clock is restored, the input bad detector waits 4
full clock periods before clearing the flag and returning to normal
operation. If CLK_SEL is changed to select a valid input clock, the
output will stay low for one full period of the new input clock, then
return to normal operation.
CLK0
CLK1
CLK_SEL
Output
Input Bad
Detect, 200ns
Figure 1D. CLK_SEL with Bad Input Timing Diagram
If the selected input clock goes bad (stuck high or low for over
approximately 200ns), an internal input bad flag is set. When the
input bad flag is set, the output goes low until the next valid clock
CLK
CLK÷2
DIV_SEL
Output
Input Bad
Detect, 200ns
event. If DIV_SEL is changed, the output will transition from the
low state following the selected divide when a valid input clock is
restored.
Figure 1E. DIV_SELx with Bad Input Timing Diagram
If the input bad flag has been set (The input has been stuck high or
low for over approximately 200ns), and OEx is pulled low, the output
will immediately go to a High-Impedance state. If the clock is restored
while the OEx is low, the output will transition from the High-
Impedance to a low state to ensure a clean rising edge of the first
output clock when the Oex is pulled high again.
CLK
OE
Output
Input Bad
Detect, 200ns
Figure 1F. OEx with Bad Input Timing Diagram
ICS870S208BKLF REVISION A APRIL 3, 2013
5
©2013 Integrated Device Technology, Inc.
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